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revision 1.00/april 2010? semtec h corp. page 1 www.semtech.com ACS8522BT esets advanced communications final synchronous equipment timing source for stratum 3/4e/4, smc and ethernet systems advanced comms & sensing final datasheet welcome to the datasheet for the semtech ACS8522BT esets integrated circuit. the electronic edition of this datasheet contains hyperlinks that are colored blue . click on a link to navigate directly to the respective topic. the ACS8522BT is a highly integrated, single-chip solution for the synchronous equipment timing source (sets) function in a sonet or sdh network element. the device generates sonet or sdh equipment clocks (sec), frame synchronization clocks and ethernet clocks. the ACS8522BT is fully compliant with the required international specifications and standards. the device supports free-run, locked and holdover modes, with mode selection controlled automatically by an internal state machine, or forced by register configuration. the ACS8522BT accepts up to four independent input sec reference clock sources from recovered line clock, pdh network, and node sync hronization. the device generates independent sec and bits clocks, an 8 khz frame synchronization clock and a 2 khz multi-frame synchronization clock (bot h with programmable pulse width and polarity) and four ethernet clocks. the ACS8522BT includes a serial port which can be spi compatible, providing access to the configuration and status registers for device setup. the ACS8522BT supports ieee 1149.1 jtag boundary scan. users can choose between ocxo or tcxo to define the stratum and/or holdover performance required. ? suitable for stratum 3, 4e, 4 and sonet minimum clock (smc) or sonet/sdh equipment clock (sec) and ethernet applications. ? meets telcordia 1244-core stratum 3 and gr-253, and itu-t g.813 options ?? and ??? and itu-t g.8262 (draft) specifications. ? accepts four individual input reference clocks, all with robust input clock source quality monitoring. ? simultaneously generates four output clocks, plus two sync pulse outputs. ? generates four ethernet frequencies (25 mhz, 50 mhz, 62.5 mhz and 125 mhz) on any combination of four to outputs. ? absolute holdover accura cy better than 3 x 10 -10 (manual), 7.5 x 10 -14 (instantaneous); holdover stability defined by ch oice of external xo. ? programmable pll bandwidth, for wander and jitter tracking/attenuation, 0.1 hz to 70 hz in 10 steps. ? automatic hit-less source switchover on loss of input. ? serial spi compatible interface. ? output phase adjustment in 6 ps steps up to 200 ns. ? ieee 1149.1 jtag boundary scan. ? single 3.3 v operation. ? available in lqfp 64-pin package. ? lead (pb)-free, halogen free, rohs and weee compliant. all standards referred to in this datasheet are listed in references and associated documents . description about this datasheet features references to standards
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 2 www.semtech.com figure 1 block diagram of the ACS8522BT esets
table of contents revision 1.00/april 2010? semtec h corp. page 3 www.semtech.com ACS8522BT esets section page advanced comms & sensing preliminary datasheet about this datasheet........................................................................................................... ...................................................................... 1 description ................................................................................................................... ..............................................................................1 features ...................................................................................................................... ...............................................................................1 references to standards ....................................................................................................... ...................................................................1 pin diagram ................................................................................................................... ............................................................................5 pin description ............................................................................................................... ............................................................................6 introduction .................................................................................................................. ..............................................................................8 overview ...................................................................................................................... ......................................................................9 general description ........................................................................................................... ........................................................................9 input reference clock ports ................................................................................................... ...................................................... 10 locking frequency modes ....................................................................................................... ............................................. 10 clock quality monitoring ...................................................................................................... .......................................................... 11 activity monitoring ....................................... .................................................................... ...................................................... 12 frequency monitoring .......................................................................................................... ................................................. 13 selection of input referenc e clock source ..................................................................................... ............................................. 14 forced control selection ...................................................................................................... ................................................. 14 automatic control selection ................................................................................................... .............................................. 14 ultra fast switching .......................................................................................................... .................................................... 14 fast external switching mode-srcsw pin ........................................................................................ .................................. 15 output clock phase continuity on so urce switchover ............................................................................ ........................... 15 modes of operation ............................................................................................................ ........................................................... 15 free-run mode ................................................................................................................. ...................................................... 15 pre-locked mode ............................................................................................................... .................................................... 16 locked mode ................................................................................................................... ...................................................... 16 lost-phase mode ............................................................................................................... .................................................... 16 holdover mode ................................................................................................................. ..................................................... 16 pre-locked2 mode .............................................................................................................. ................................................... 19 dpll architecture and configuration .................... ....................................................................... ................................................ 19 to dpll main features ......................................................................................................... ............................................... 20 t4 dpll main features ......................................................................................................... ............................................... 20 to dpll automatic bandwidth controls .................. ........................................................................ .................................... 20 phase detectors ............................................................................................................... ..................................................... 20 phase lock/loss detection ..................................................................................................... ............................................. 21 damping factor programmability .......................... ...................................................................... ......................................... 21 local oscillator clock ..................................... ................................................................... .................................................... 22 output wander ................................................................................................................. ..................................................... 22 jitter and wander transfer .................................................................................................... ............................................... 25 phase build-out ............................................................................................................... ...................................................... 25 input-to-output phase adjustment .............................................................................................. ......................................... 26 input wander and jitter tolerance ..................... ........................................................................ .......................................... 26 using the dplls for accurate frequency and phase report ing .................................................................... .................... 28 mfrsync and frsync alignment-sync2k .................... ....................................................................... .................................. 29 output clock ports ............................................................................................................ ............................................................. 29 pecl/lvds output port selection ........................ ....................................................................... ........................................ 30 output frequency selection and conf iguration .................................................................................. ................................ 30 power-on reset ................................................................................................................ .............................................................. 42 serial interface .............................................................................................................. ................................................................. 42 register map .................................................................................................................. ......................................................................... 45 register organization ......................................................................................................... ........................................................... 45 multi-word registers .......................................................................................................... ................................................... 45 register access ............................................................................................................... ...................................................... 45 interrupt enable and clear .................................................................................................... ............................................... 45 defaults ...................................................................................................................... ............................................................ 45 register descriptions ......................................................................................................... .................................................................... 49
revision 1.00/april 2010? semtec h corp. page 4 www.semtech.com ACS8522BT esets section page advanced comms & sensing preliminary datasheet electrical specifications ..................................................................................................... .................................................................. 109 jtag .......................................................................................................................... .................................................................... 109 over-voltage protection ....................................................................................................... ........................................................ 109 esd protection ................................................................................................................ ............................................................. 109 latchup protection ............................................................................................................ ........................................................... 109 maximum ratings ............................................................................................................... ......................................................... 110 operating conditions .......................................................................................................... ......................................................... 110 dc characteristics ............................................................................................................ ........................................................... 110 jitter performance ............................................................................................................ ........................................................... 113 input/output timing ........................................................................................................... ......................................................... 115 package information ........................................................................................................... ................................................................. 116 thermal conditions ............................................................................................................ .......................................................... 116 application information ... .................................................................................................... ................................................................. 118 references and associated document s ........................................................................................... .................................................. 119 acronyms and abbreviations .................................................................................................... ........................................................... 119 trademark acknowledgements .................................................................................................... ....................................................... 120 revision status/history .......... ............................................................................................. ................................................................ 121 ordering information .......................................................................................................... .................................................................. 122 disclaimers ................................................................................................................... ................................................................ 122 contact information ........................................................................................................... ................................................................... 122
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 5 www.semtech.com figure 2 ACS8522BT pin diagram synchr onous equipment timing source for stratum 3/4e/4, smc and ethernet systems pin diagram
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 6 www.semtech.com note...i = input, o = output, p = power, ttl u = ttl input with pull-up resistor, ttl d = ttl input with pull-down resistor. pin description table 1 power pins pin number symbol i/o type description 8, 9, 12 vd1+, vd2+, vd3+ p - digital supply to gates in analog section, +3.3 v (10%). 22 vdd_diff p - digital supply for differential output pins 19 and 20, +3.3 v (10%). 27 vdd5v p - digital supply for +5 v tolerance to input pins. connect to +5 v (10%) for clamping to +5 v. connect to vdd for clamping to +3.3 v. leave floating for no clamping, input pins tolerant up to +5.5 v. 32, 36, 38, 39, 45, 46, 54 vdd1, vdd2, vdd3, vdd4, vdd5, vdd6, vdd7 p - digital supply to logic, +3.3 v (10%). 4 va1+ p - analog supply to clock multiplying pll, +3.3 v (10%). 14, 57 va2+, va3+ p - analog supply to outp ut plls apll2 and apll1, +3.3 v (10%). 15, 58 agnd3, agnd4 - analog ground for output plls apll2 and apll1. 7, 10, 11 dgnd1, dgnd2, dgnd3 p - digital ground for components in plls. 31, 40, 53 dgnd4, dgnd5, dgnd6 p - digital ground for logic. 21 gnd_diff p - digital ground for differential output pins 19 and 20. 1, 3 agnd1, agnd2 p - analog grounds. table 2 internally connected pins pin number symbol i/o type description 2, 16, 23, 24, 25, 26, 35, 60, 61, 62, 63 ic1, ic2, ic3, ic4, ic5, ic6, ic7, ic8, ic9, ic10, ic11 - - leave to float.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 7 www.semtech.com table 3 other pins pin number symbol i/o type description 5intreqottl/cmosactive high / low software interrupt request output. 6 refclk i ttl 12.800 mhz reference clock (refer to local oscillator clock ). 13 srcsw i ttl d force fast source switching on sec1 and sec2. 17 frsync o ttl/cmos 8 khz frame sync reference output. 18 mfrsync o ttl/cmos 2 khz multi-frame sync reference output. 19, 20 o1pos, o1neg o lvds/pecl output referenc e, programmable, default 38.88 mhz, lvds. 28 sync2k i ttl d multi-frame sync 2khz input. 29 sec1 i ttl d input reference, progra mmable, default 8 khz. 30 sec2 i ttl d input reference, progra mmable, default 8 khz. 33 sec3 i ttl d input reference, progra mmable, default 19.44 khz. 34 sec4 i ttl d input reference, progra mmable, default 19.44 khz. 37 trst i ttl d jtag control reset input. 1 = enable jtag boundary scan mode. 0 = boundary scan standby mode allowing correct device operation. if not used connect to gnd or leave floating. 41 tms i ttl d jtag test mode select: boundary scan enable. sampled on rising edge of tck. if not used connect to vdd or leave floating. 42 clke i ttl d sclk edge select: sclk active edge select, clke = 1, selects falling edge of sclk to be active. 43 sdi i ttl d microprocessor interface address: serial data input. 44 csb i ttl u chip select (active low ): this pin is asserted low by the microprocessor to enable the microprocessor interface. 47 sclk i ttl d serial data clock. when this pin goes high data is latched from sdi pin. 48 porb i ttl u power-on reset: master reset. if porb is forced low , all internal states are reset back to default values. 49 tck i ttl d jtag clock: boundary scan clock input. 50 tdo o ttl/cmos jtag output: serial test data output. updated on falling edge of tck. 51 tdi i ttl d jtag input: serial test data input. sampled on rising edge of tck. 52 sdo o ttl d interface address: spi compatible serial data output. 55 o2 o ttl/cmos output reference 2, programmable, default 38.88 mhz. 56 o3 o ttl/cmos output reference 3, programmable, default 19.44 mhz. 59 o4 o ttl/cmos output reference 4, progra mmable, default 1.544/2.048 mhz (bits). 64 sonsdhb i ttl d sets the initial power-up or porb state of the sonet/sdh frequency selection registers, reg. 34 bit 2, and reg. 38 bits 5 and 6. when set low , sdh rates are selected (2.048 mhz etc.), and when set high , sonet rates are selected (1.544 mhz etc.). the register states can be changed after power-up by software.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 8 www.semtech.com the ACS8522BT is a highly integrated, single-chip solution for the sets function in a sonet/sdh/ethernet network element, for the generation of sec and frame/multiframe sync pulses. digital phase locked loop (dpll) and direct digital sy nthesis methods are used in the device so that the overal l pll characteristics are very stable and consistent compar ed to traditional analog plls. in free-run mode, the acs8522 bt generates a stable, low- noise clock signal at a freque ncy to the same accuracy as the external oscillator, or it can be made more accurate via software calibration to within 0.02 ppm in locked mode, the ACS8522BT selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. in holdover mode, the ACS8522BT generates a stable, low-noise clock signal, adjust ed to match the last known good frequency of the last selected reference source. a high level of phase and frequency accuracy is made possible by an internal resolution of up to 54 bits and internal holdover accuracy of 0.0012 ppb (1.2 x 10 -12 ). in all modes, the frequency accuracy, jitter and drift performance of the clock meet the requirements of: itu g.736 g.742 g783 g.812 g.813 g.823 g.824 and telcordia gr-253-core gr-1244-core itu-t g.8262 (draft). the ACS8522BT supports all three types of reference clock source: recovered li ne clock, pdh network synchronization timing and node synchronization. the ACS8522BT generates independent t0 and t4 clocks, an 8 khz frame synchronization clock and a 2 khz multi-frame synchronization clock. a significant architectural advantage of the ACS8522BT over traditional solutions is the use of dpll technology for precise and repeatable performance over temperature or voltage variations, and between parts. the overall pll bandwidth, loop damping, pull-in range and frequency accuracy are all determined by digital parameters that provide a consistent level of performance. an analog pll (apll) takes the signal from the dpll output and provides a lowe r jitter output. the apll bandwidth is set four orders of magnitude higher than the dpll bandwidth. this ensures that the overall system performance still maintains the advantage of consistent behavior provided by the digital approach. the dplls are clocked by the external oscillator module (tcxo or ocxo) so that th e free-run or holdover frequency stability is only de termined by the stability of the external oscillator module . this second key advantage confines all temperature critical components to one well defined and pre-calibrated module, whose performance can be chosen to match the application; for example an tcxo for stratum 3 applications. all performance parameters of the dplls are programmable without the need to understand detailed pll equations. bandwidth, da mping factor and lock range can all be set directly, for example. the pll bandwidth can be set over a wide range, 0.1 hz to 70 hz in 18 steps, to cover all sonet/sdh clock synchronization applications. the ACS8522BT includes a serial port, providing access to the configuration and status registers for device setup and monitoring. introduction
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 9 www.semtech.com overview please refer to figure 1 . the ACS8522BT sets device has four sec clock inputs (sec1 to sec4), and generate s four output clocks on outputs o1 to o4. the device offers a total of 55 possible output frequencies. there are two independent paths through the device: t0 path comprising t0 dpll and t0 output and feed- back aplls; t4 path comprising t4 dpll and t4 output apll. the t0 path is a high qualit y, highly configurable path designed to provide features necessary for node timing synchronization within a so net/sdh network. the t4 path is a simpler and less configurable path designed to give a totally independent route for internal equipment synchronization. the device supports use of either or both paths, locked togeth er or independent. the four sec inputs ports are ttl/cmos, 3 v and 5 v compatible (with clamping if required by connecting the vdd5v pin). refer to electrical specifications for more information on the electrical compatibility and details. input frequencies supported range from 2 khz to 100 mhz. common e1, ds1, oc3 and su b-divisions are supported as spot frequencies to which the dplls will directly lock. any input frequency, up to 100 mhz, that is a multiple of 8 khz can also be locked to via an inbuilt programmable divider. an input reference monitor is assigned to each of the four inputs. the monitors operate continuously such that at all times the status of all of the inputs to the device are known. each input can be monitored for both frequency and activity, activity alone, or the monitors can be disabled. the frequency monitors have a ?hard? (rejection) alarm limit and a ?soft? (flag only) alarm limit for monitoring frequency, whilst the referenc e is still within its allowed frequency band. each input reference can be programmed with a priority number allowing references to be chosen according to the highest priority valid input. the two paths (t0 and t4) have independent priorities to allow completely independent operation of the two paths. both paths operate automatic or external source selection. for automatic input reference selection, the t0 path has a more complex state machine than the t4 path. the t0 and t4 pll paths support the following common features: ? automatic source selection according to input priorities and quality level. ? different quality levels (activity alarm thresholds) for each input. ? variable bandwidth, lock range and damping factor. ? direct pll locking to common sonet/sdh input frequencies or any integer multiple of 8 khz up to 100 mhz. ? automatic mode switching between free-run, locked and holdover states. ? fast detection on input fail ure and entry into holdover mode (holds at the last good frequency value). ? frequency translation between input and output rates via direct digital synthesis. ? high accuracy digital architecture for stable pll dynamics combined with an apll for low jitter final output clocks. a number of features supported by the t0 path are not supported by the t4 path, although these features can also all be externally controlled by software. the additional features of the t0 path are: ? non-revertive mode. ? phase build-out on source switch (hit-less source switching). ? i/o phase offset control. ? greater programmable bandwidth from 0.1 hz to 70 hz in 10 steps (the bandwidth of the t4 path is programmable in 3 steps: 18 hz, 35 hz and 70 hz). ? noise rejection on low frequency input. ? manual holdover frequency control. ? controllable automatic holdover frequency filtering. ? frame sync pulse alignment. the operation of the dpll in the t0 path is controlled by software or an internal state machine. the state machine for the t4 path is very simple and cannot be manually/externally contro lled, however the overall operation can be controlled by manual reference source selection. an additional feature of the t4 path is the ability to measure a phase difference between two inputs. general description
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 10 www.semtech.com the dpll of the t0 path always produces an output at 77.76 mhz to feed the apll, regardless of the frequency selected at the output pins. the t4 path can be operated at a number of frequencies. this is to enable the generation of extra output frequencies, which cannot be easily related to 77.76 mhz. when the t4 path is selected to lock to the t0 path, the t4 dpll locks to the 8 khz from the t0 dpll. this is because all of the frequencies of operation of the t4 path can be divided to 8 khz and this will ensure synchronization of all the frequencies within the two paths. the outputs of both dplls are connected to multiplying and filtering aplls. the output s of the aplls are divided, making a number of frequencies simultaneously available for selection at the output clock ports. the various combinations of dpll, apll and divider configurations allow for generation of a comprehensive set of frequencies as listed in table 12 . to synchronize the lower outp ut frequencies when the t0 pll is locked to a high frequency reference input, an additional input is provided. the sync2k pin (pin 28) is used to reset the dividers that generate the 2 khz and 8 khz outputs such that the output 2/8 khz clocks are lined up with the input 2 khz. this synchronization method could allow for example, a master and a slave device to be in precise alignment. the ACS8522BT also supports sync pulse references of 4 khz or 8 khz, although frequencies lower than the sync pulse reference may not necessarily be in phase. input reference clock ports table 4 gives details of the inpu t reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. note that sdh and sonet networks use different default frequencies; the network type is pin-selectable (using either the sonsdhb pin or via software). specific frequencies and priorities are set by configuration. the input ports are fully interchangeable. sdh and sonet networks use different default frequencies; the network type is selectable using cnfg_input_mode reg. 34, bit 2 ip_sonsdhb . for sonet, ip_sonsdhb = 1 for sdh, ip_sonsdhb = 0 on power-up or by reset, the default will be set by the state of the sonsdhb pin (pin 64). specific frequencies and priorities are set by configuration. the frequency selection is programmed via the cnfg_ref_source_frequency register (reg. 22, 22, 27 and 28). locking frequency modes there are three locking frequency modes that can be configured: direct lock lock 8k divn direct lock mode in direct lock mode, the internal dpll can lock to the selected input at the spot frequency of the input, for example 19.44 mhz performs the dpll phase comparisons at 19.44 mhz. in lock8k and divn modes an internal divider is used prior to the dpll to divide the input frequency before it is used for phase comparisons in the dpll. lock8k mode lock8k mode automatically sets the divider parameters to divide the input frequency down to 8 khz. lock8k can only be used on the supported spot frequencies (see table 4 note(i)). lock8k mode is enabled by setting the lock8k bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. using lower freque ncies for phase comparisons in the dpll results in a greater tolerance to input jitter. it is possible to choose which edge of the input reference clock to lock to, by setting 8k edge polarity (bit 2 of reg. 03, test_register1.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 11 www.semtech.com note: (i) ttl ports (compatible also with c mos signals) support clock speeds up to 100 mhz, with the highes t spot frequency bein g 77.76 mhz. the actual spot frequencies are: 2 khz, 4 khz, 8 khz (and n x 8 khz), 1.544 mhz (sonet)/2.048 mhz (sdh), 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz. sonet or sdh input ra te is selected via reg. 34 bit 2, ip_sonsdhb). divn mode in divn mode, the divider parameters are set manually by configuration (bit 7 of the cnfg_ref_source_frequency register), but must be set so that the frequency after division is 8 khz. the divn function is defined as: divn = ?divide by n+ 1?, i.e. it is the dividing factor used for the division of the input frequency, and has a value of (n+1) where n is an integer from 1 to 12499 inclusive. therefore, in divn mode the input frequency can be divided by any integer value between 2 to 12500. consequently, any input frequency which is a multiple of 8 khz, between 8 khz to 100 mhz, can be supported by using divn mode. note...any reference input can be set to use divn independently of the frequencies and configurations of the other inputs. however only one va lue of n is allowed, so all inputs with divn selected mu st be running at the same frequency. divn examples (a) to lock to 2.000 mhz: (i) set the cnfg_ref_source_frequency register to 10xx0000 (binary) to enable divn, and set the frequency to 8 khz - the frequency required after division. (xx = ?leaky bucket? id for this input). (ii) to achieve 8 khz, the 2 mhz input must be divided by 250. so, if divn = 250 = (n + 1) then n must be set to 249. this is done by writing f9 hex (249 decimal) to the divn register pair reg. 46/47. (b) to lock to 10.000 mhz: (i) the cnfg_ref_source_frequency register is set to 10xx0000 (binary) to set the divn and the frequency to 8 khz, the post-division frequency. (xx = ?leaky bucket? id for this input). (ii) to achieve 8 khz, the 10 mhz input must be divided by 1250. so, if divn, = 1250 = (n+1) then n must be set to 1,249. this is done by writing 4e1 hex (1,249 decimal) to the divn register pair reg. 46/47. clock quality monitoring clock quality is monitored and used to modify the priority tables. the following parameters are monitored: 1. activity (toggling). 2. frequency (this monitoring is only performed when there is no irregular operat ion of the clock or loss of clock condition). any reference source that suffers a loss-of-activity or clock-out-of-band condition will be declared as unavailable. clock quality monitoring is a continuous process which is used to identify clock proble ms. there is a difference in dynamics between the selected clock and the other reference clocks. anomalies occurring on non-selected reference sources affect only that source's suitability for selection. table 4 input reference source selection and priority table input port channel number (bin) input port technology frequencies supported default priority sec1 0011 ttl/cmos up to 100 mhz (see note (i)) default (sonet): 8 khz default (sdh): 8 khz 2 sec2 0100 ttl/cmos up to 100 mhz (see note (i)) default (sonet): 8 khz default (sdh): 8 khz 3 sec3 1000 ttl/cmos up to 100 mhz (see note (i)) default (sonet): 19.44 mhz default (sdh): 19.44 mhz 4 sec4 1001 ttl/cmos up to 100 mhz (see note (i)) default (sonet): 19.44 mhz default (sdh): 19.44 mhz 5
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 12 www.semtech.com anomalies occurring on the selected clock could have a detrimental impact on the accuracy of the output clock. anomalies detected by the activity detector are integrated in a leaky bucket accumulator. occasional anomalies do not cause the accumulator to cross the alarm setting threshold, so the selected re ference source is retained. persistent anomalies cause th e alarm setting threshold to be crossed and result in th e selected reference source being rejected. anomalies on the currently locked-to input reference clock, whether affecting signal purity or signal frequency, could induce jitter or frequency offsets in the output clock, leading to anomalous behavior. anomalies on the selected clock, therefore, have to be detected as they occur and the phase locked loop must be temporarily isolated until the clock is once again pure. the clock monitoring process cannot be used for this because the high degree of accuracy required dictates that the process be slow. to achieve the immediacy required by the phase locked loop requires an alternative mechanism. the phase locked loop itself contains a fast activity detector such that within approximately two missing input clock cycles, a no-activity flag is raised and the dpll is frozen in holdover mode. this flag can also be read as the main_ref_failed bit (from reg. 06, bit 6) and can be set to indicate a phase lost state by enabling reg. 73, bit 6. with the dpll in holdover mode it is isolated from further disturbances. if the input becomes available again before the activity or frequency monitor rejection alarms have been raised, then the dpll will continue to lock to the input, with little disturbance. in this scenario, with the dpll in the ?locked? state, the dpll uses ?nearest edge locking? mode (180 capture) avoiding cycle slips or glitches caused by trying to lock to an edge 360 away, as would happen with traditional plls. activity monitoring the ACS8522BT has a combined inactivity and irregularity monitor. the ACS8522BT uses a leaky bucket accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. such integrators are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. even ts which are sufficiently spread out should not trigger the alarm. by adjusting the alarm setting threshold, the point at which the alarm is triggered can be controlled. the point at which the alarm is cleared depends upon the decay rate and the alarm clearing threshold. on the alarm setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur further apart, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually . if events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. on the alarm clearing side, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarm clearing threshold. the ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. this means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). see figure 3 . there is one leaky bucket accumulator per input channel. each leaky bucket can select from four configurations (leaky bucket configuration 0 to 3). each leaky bucket configuration is programmable for size, alarm set and reset thresholds, and decay rate. each source is monitored over a 128 ms period. if, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the accumulator is incremented. the accumulator will continue to increment up to the point that it reaches the prog rammed bucket size. the ?fill rate? of the leaky bucket is, therefore, 8 units/second. the ?leak rate? of the leaky bucket is programmable to be in multiples of the fill rate (x 1, x 0.5, x 0.25 and x 0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. a conflict between trying to ?leak? at the same time as a ?fill? is avoided by preventing a leak when a fill event occurs. disqualification of a non-se lected reference source is based on inactivity, or on an out-of-band result from the frequency monitors. the currently selected reference source can be disqualified for phase, frequency, inactivity or if the source is outside the dpll lock range. if the currently selected reference source is disqualified, the next highest priority, qual ified reference source is selected.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 13 www.semtech.com interrupts for activity monitors the loss of the currently sele cted reference source will eventually cause the input to be considered invalid, triggering an interrupt, if not masked. the time taken to raise this interrupt is depe ndent on the leaky bucket configuration of the activity monitors. the fastest leaky bucket setting will still take up to 128 ms to trigger the interrupt. the interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source failure detection if desired. it is triggered after missing just a couple of cycles of the reference source. some applicat ions require the facility to switch downstream devices ba sed on the status of the reference sources. in order to pr ovide extra flexibility, it is possible to flag the main_ref_failed interrupt (reg. 06 bit 6) on the pin tdo. this is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. the bit is re set by writing to the interrupt status register in the normal way. this feature can be enabled and disabled by writing to reg. 48 bit 6. figure 3 inactivity and irregularity monitoring leaky bucket timing the time taken (in seconds) to raise an inactivity alarm on a reference source that has pr eviously been fully active (leaky bucket empty) will be: (cnfg_upper_threshold_n) / 8 where n is the number of the leaky bucket configuration. if an input is intermittently in active then this time can be longer. the default setting of cnfg_upper_threshold is 6, therefore the default time is 0.75 s. the time taken (in seconds) to cancel the activity alarm on a previously completely inactive reference source is calculated, for a partic ular leaky bucket, as: [2 (a) x (b - c)]/ 8 where: a = cnfg_decay_rate_n b = cnfg_bucket_size_n c = cnfg_lower_threshold_n (where n = the number of the relevant leaky bucket configuration in each case). the default setting is shown in the following: [2 1 x (8 - 4)] /8 = 1.0 secs frequency monitoring the ACS8522BT performs input frequency monitoring to identify reference sources wh ich have drifted outside the acceptable frequency range measured with respect either to the output clock or to the xo clock. the sts_reference_sources out-of-band alarm for a particular reference source is raised when the reference source is outside the acceptable frequency range. with the default register settings a soft alarm is raised if the drift is outside 11.43 ppm and a hard alarm is raised if the drift is outside 15.24 ppm. both of these limits are programmable from 3.8 ppm up to 61 ppm. inactivities/irregularities programmable fall slopes reference source leaky bucket response alarm bucket_size upper_threshold lower_threshold (all programmable)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 14 www.semtech.com the ACS8522BT dpll has a programmable lock and capture range frequency limit up to 80 ppm (default is 9.2 ppm). selection of input reference clock source under normal operation, the input reference sources are selected automatically by an order of priority. but, for special circumstances, such as chip or board testing, the selection may be forced by configuration. automatic operation selects a reference source based on its pre-defined priority and its current availability. a table is maintained which lists all reference sources in the order of priority. this is initially defined by the default configuration and can be changed via the serial interface by the network manager. in this way, when all the defined sources are active and valid, the source with the highest programmed priority is selected but, if this source fails, the next-highest source is selected, and so on. restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. for this, the ACS8522BT has two modes of operation; revertive and non-revertive. in revertive mode, if a re-val idated (or newly validated) source has a higher priority than the reference source which is currently selected, a switch over will take place. many applications prefer to minimize the clock switching events and choose non-revertive mode. in non-revertive mode, when a re-validated (or newly validated) source has a higher priority then the selected source will be maintained. the re-validation of the reference source will be flagged in the sts_sources_valid register (reg. 0e and 0f) and, if not masked, will generate an interrupt. selection of the re-validated source can take place under software control or if the currently selected source fails. to enable software control, the software should briefly enable revertive mode to e ffect a switch-over to the higher priority source. when there is a reference available with higher priority than the selected reference, there will be no change of reference source as long as the non-revertive mode remains on, and the currently selected source is valid. a failure of the selected reference will always trigger a switch-over regardless of whether revertive or non- revertive mode has been chosen. forced control selection a configuration register, force_select_reference_source reg. 33, controls both the choice of automatic or forced selection and the selection itse lf (when forced selection is required). for automatic choice of source selection, the four lsb bit value is set to a ll zeros or all ones (default). to force a particular input the bit value must be set as follows: 0011 forces sec1, 0100 forces sec2, 1000 forces sec3 and 1001 forces sec4. forced selection is not the normal mode of operation, and the force_select_reference_source variable is defaulted to the all-one value on reset, thereby adopting the automatic selection of the reference source. automatic control selection when an automatic selection is required, the force_select_reference_source register lsb four bits must be set to all zeros or all ones. the configuration registers, cnfg_ref_selection_priority ( reg. 19 , 1b and 1c), hold 4-bit values which represents the desired priority of that particular port. unused ports should be given the value 0000 in the relevant register to indicate they are not to be included in the priority table. on power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined by table 4. the selection priori ty values are all relative to each other, with lower-valued numbers taking higher priorities. each reference source should be given a unique number; the valid values are 1 to 15 (dec). a value of zero disables the reference source. however if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. if the first of two same priority number sour ces goes invalid the second will be switched in. if the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. if a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. there is no implied priori ty based on the channel numbers. revertive/non-revert ive mode has no effect on sources with the same priority value. ultra fast switching a reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. an option for a faster disqualification has been implemented, whereby if reg. 48 bit 5 ( ultra_fast_switch ) is set, then a loss of activity of just a few reference clock cycles will set the main_ref_failed alarm and cause a reference switch.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 15 www.semtech.com this can be configured (see reg. 06, bit 6) to cause an interrupt to occur instead of , or as well as, causing the reference switch. the sts_interrupts register reg. 06 bit 6 ( main_ref_failed ) is used to flag inactivity on the reference that the device is locked to much faster than the activity monitors can support. if reg. 48 bit 6 of the cnfg_monitors register ( los_flag_on_tdo ) is set, then the state of this bit is driven onto the tdo pin of the device. note...the flagging of the loss of the main reference failure on tdo is simply allowing the stat us of the sts_interrupts bit main_ref_failed (reg. 06 , bit 6) to be reflected in the state of the tdo output pin. the pin will, therefore, remain high until the interrupt is cleare d. this functionality is not enabled by default so the usual jtag functions can be used. when the tdo output from the ACS8522BT is connected to the tdi pin of the next device in the jtag scan chain, the implementation should be such that a logic chan ge caused by the action of the interrupt on the tdi input should not effect the operation when jtag is not active. fast external switch ing mode-srcsw pin fast external switching mo de allows fast switching between inputs sec1 and sec2 only. the mode must first be enabled before switching can take place, and then switching is controlled via the srcsw pin. there are two ways to enable fast external switching mode: ? mode enable by register wr ite - by writing to reg. 48 bit 4, or ? mode enable by hardware ?i nitialization? - by holding srcsw high throughout reset and for at least a further 251 ms after porb has gone high (250 ms allowance for the internal reset to be removed plus 1 ms allowance for aplls to start-up and become stable). a simple external ci rcuit to set scrsw high for the required period is shown in ?simplified application schematic? on page 118. if scrsw pin is held low at any time during the 251 ms initialization period, this may result in fast external switching mode not being enabled correctly. once fast external switching mode is enabled, then the value of the srcsw pin directly selects either sec1 (srcsw high ) or sec2 (srcsw low ). if this mode is enabled by hardware initializa tion, then it configures the default frequency toleranc e of sec1 and sec2 to 80 ppm (reg. 41 and 42). either of these registers can be subsequently reconfigured by external software, if required. when fast external switch ing mode is enabled, the device operates as a simple switch. all clock monitoring is disabled and the dpll will simply be forced to try to lock on to the indicated reference source. consequently the device will always indicate ?locked? state in the sts_operating register (reg. 09, bits 2:0). output clock phase co ntinuity on source switchover if either pbo is selected on (default), or, if dpll frequency limit is set to less than 30 ppm or (9.2 ppm default), the device will always comply with gr-1244-core [19] specification for stratum 3 (maximum rate of phase change of 81 ns/1.326 ms), for all input frequencies. modes of operation the ACS8522BT has three primary modes of operation (free-run, locked and holdover) supported by three secondary, temporary modes (p re-locked, lost-phase and pre-locked2). these are shown in the state transition diagram, figure 4. the ACS8522BT can operate in forced or automatic control. on reset, the ACS8522BT reverts to automatic control, where transitions between states are controlled completely automatically. forc ed control can be invoked by configuration, allowing transitions to be performed under external control. this is not the normal mode of operation, but is provided fo r special occasions such as testing, or where a high degr ee of hands-on control is required. free-run mode the free-run mode is typically used following a power-on- reset or a device reset before network synchronization has been achieved. in the free-run mode, the timing and synchronization signals gene rated from the ACS8522BT are based on the 12.800 mhz clock frequency provided from the external oscillator and are not synchronized to an input reference source. by default, the frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the oscillator. however the external oscillator frequency can be calibrated to improve its accuracy by a software calibration routine using register cnfg_nominal_frequency (reg. 3c and 3d). for example a 500 ppm offset crystal could be made to look like one accurate to within 0.02 ppm.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 16 www.semtech.com the transition from free-run to pre-locked occurs when the ACS8522BT selects a reference source. pre-locked mode the ACS8522BT will enter the locked state in a maximum of 100 seconds, as defined by gr-1244-core [19] specification, if the selected reference source is of good quality. if the device cannot achieve lock within 100 seconds, it reverts to fr ee-run mode and another reference source is selected. locked mode the locked mode is entered from pre-locked, pre-locked2 or phase-lost mode when an input reference source has been selected and the dpll has locked. the dpll is considered to be locked when the phase loss/lock detectors indicate that the dpll has remained in phase lock continuously for at least one second (see phase lock/loss detection ). when the acs8530 is in locked mode, the output frequency and phase track the selected input reference source. lost-phase mode lost-phase mode is used whenever the phase loss/lock detectors indicate that the dpll has lost phase lock (see phase lock/loss detection ). the dpll will still be trying to lock to the input clock referenc e, if it exists. if the leaky bucket accumulator calculates that the anomaly is serious, the device disqualifies the reference source. if the device spends more than 100 seconds in lost-phase mode, the reference is disqua lified and a phase alarm is raised on it. if the reference is disqualified, one of the following transitions takes place: 1. go to pre-locked2; - if a known good stand-by source is available. 2. go to holdover; - if no stand-by sources are available. holdover mode holdover mode is the operating condition the device enters when its currently selected input source becomes invalid, and no other valid replacement source is available. in this mode, the de vice resorts to using stored frequency data, acquired when the input reference source was still valid, to control its output frequency. in holdover mode, the acs 8522bt provides the timing and synchronization signals to maintain the network element but is not phase-locked to any input reference source. its output frequency is determined by an averaged version of the dpll frequency when last in the locked mode. holdover can be configured to operate in: ? automatic mode (reg. 34 bit 4, cnfg_input_mode: man_holdover set low ), or ? manual mode (reg. 34 bit 4, cnfg_input_mode: man_holdover set high ). automatic mode in automatic mode, the devi ce can be configured to operate using: ? averaged - (reg. 40 bit 7, cnfg_holdover_modes, auto_averaging: set high ), or ? instantaneous - (reg. 40 bit 7, cnfg_holdover_modes, auto_averaging: set low ). averaged in the averaged mode, the frequency (as reported by sts_current_dpll_frequency , see reg. 0c, 0d and 07) is filtered internally using an infinite impulse response filter, which can be set to: ? fast - (reg. 40 bit 6, cnfg_holdover_modes, fast_averaging: set high ), giving a -3 db filter response point correspo nding to a period of approximately eight minutes, or ? slow - (reg. 40 bit 6, cnfg_holdover_modes, fast_averaging: set low ) giving a -3 db filter response point corresponding to a period of approximately 110 minutes. instantaneous in instantaneous mode, the dp ll freezes at the frequency it was operating at the time of entering holdover mode. it does this by using only its internal dpll integral path value (as reported in reg. 0c, 0d and 07) to determine output frequency. the dpll prop ortional path is not used so that any recent phase disturbances have a minimal effect on the holdover frequency. the integral value used can be viewed as a filtered version of the locked output frequency over a short period of time. the period being in inverse proportion to the dpll bandwidth setting.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 17 www.semtech.com manual mode (reg. 34 bit 4, cnfg_input_mode , man_holdover set high .) the holdover frequency is determined by the value in register cnfg_holdover_frequency (reg. 3e, 3f, and part of 40). this is a 19-bit signed number, with a lsb resolution of 0.0003068 ppm, which gives an adjustment range of 80 ppm. the value can be derived from a reading of the register sts_current_dpll_frequency (reg. 0c, 0d and 07), which gives, in the same format, an indication of the current output frequency deviation, which would be read when the device is locked. if required, this value could be read by external software and averaged over time. the averaged value could then be fed to the cnfg_holdover_frequency register, ready for setting the averaged frequency value when the device enters holdover mode. the sts_current_dpll_frequency value is internally derived from the dpll integral path, which represents a short-term average measure of the current frequency, depending on the locked loop bandwidth (reg. 67) selected. it is also possible to combine the internal averaging filters with some additional software filtering. for example the internal fast filter could be us ed as an anti-aliasing filter and the software could further filter this before determining the actual holdov er frequency. to support this feature, a facility to read out the internally averaged frequency has been provided.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 18 www.semtech.com figure 4 automatic mode control state diagram free-run select ref (state 001) (1) reset (3) no valid standby ref & (main ref invalid or out of lock > 100s (2) all refs evaluated & at least one ref valid pre-locked wait for up to 100s (state 110) (4) valid standby ref & [main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock > 100s] (5) selected ref phase locked locked keep ref (state 100) lost-phase wait for up to 100s (state 111) (10) selected source phase locked (6) no valid standby ref & main ref invalid (7) phase lost on main ref (8) phase regained within 100s (9) valid standby ref & [main ref invalid or (higher priority ref valid & in revertive mode)] pre-locked2 wait for up to 100s (state 101) holdover select ref (state 010) (12) valid standby ref & (main ref invalid or out of lock >100s) (11) no valid standby ref & (main ref invalid or out of lock >100s) (15) valid standby ref & [main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] (13) no valid standby ref & (main ref invalid or out of lock >100s) (14) all refs evaluated & at least one ref valid reference sources are flagged as valid when active, in-band and have no phase alarm set. all sources are continuously checked for activity and frequency only the main source is checked for phase. a phase lock alarm is only raised on a reference when that reference has lost phase whilst being used as the main reference. the micro-processor can reset the phase lock alarm. a source is considered to have phase locked when it has been continuously in phase lock for between 1 and 2 seconds. f8530d_018automodecontstatedia_02
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 19 www.semtech.com by setting reg. 40, bit 5, cnfg_holdover_modes , read_average, the value read back from the cnfg_holdover_frequency register will be the filtered value. the filtered value is available regardless of what actual holdover mode is selected. clearly this results in the register not reading back the data that was written to it. example: software averaging to eliminate temperature drift. select manual holdover mode by setting reg. 34 bit 4, cnfg_input_mode, man_holdover high . select fast holdover averag ing mode by setting reg. 40 bit 6, cnfg_holdover_modes , auto_averaging high and reg. 40 bit 7 high . select to be able to read back filtered output by setting reg. 40 bit 5, cnfg_holdover_modes , read_average high . software periodically read s averaged value from the cnfg_holdover_frequency register and the temperature (not supplied from ACS8522BT). software processed frequency and temperature and places data in software look-up table or other algorithm. software writes back appropriate averaged value into the cnfg_holdover_frequency register. once holdover mode is ente red, software periodically updates the cnfg_holdover_frequency register using the temperature information (not supplied from ACS8522BT). mini-holdover mode holdover mode so far described refers to a state to which the internal state machine switches as a result of activity or frequency alarms, and this state is reported in reg. 09. to avoid the dpll?s frequency being pulled off as a result of a failed input, then the dpll has a fast mechanism to freeze its current frequency within one or two cycles of the input clock source stopping . under these circumstances the dpll enters mini-holdover mode; the mini-holdover frequency used being determined by reg. 40, bits [4:3], cnfg_holdover_modes , mini_holdover_mode. mini-holdover mode only lasts until one of the following occurs: ? a new source has been selected, or ? the state machine enters holdover mode, or ? the original fault on the input recovers. external factors affe cting holdover mode if the external tcxo/ocxo frequency is varying due to temperature fluctuations in the room, then the instantaneous value can be different from the average value, and then it may be possible to exceed the 0.05 ppm limit (depending on how extreme the temperature fluctuations are). it is advantageous to shield the tcxo/ocxo to sl ow down frequency changes due to drift and external temperature fluctuations. the frequency accuracy of holdover mode has to meet the itu-t, etsi and telcordia performance requirements. the performance of the external oscillator clock is critical in this mode, although only the frequency stability is important - the stability of the output clock in holdover is directly related to the stability of the external oscillator. pre-locked2 mode this state is very similar to the pre-locked state. it is entered from the holdover state when a reference source has been selected and applied to the phase locked loop. it is also entered if the devi ce is operating in revertive mode and a higher-priority re ference source is restored. upon applying a reference source to the phase locked loop, the ACS8522BT will enter the locked state in a maximum of 100 seconds, as defined by gr-1244-core specification, if th e selected reference source is of good quality. if the device cannot achieve lock within 100 seconds, it reverts to holdover mode and another reference source is selected. dpll architecture and configuration a dpll gives a stable and consistent level of performance that can be easily programmed for different dynamic behavior or operating range. it is not affected by operating conditions or silicon process variations. digital synthesis is used to generate all required sonet/sdh output frequencies. the digital logi c operates at 204.8 mhz that is multiplied up from the external 12.800 mhz oscillator module. hence the best resolu tion of the output signals from the dpll is one 204.8 mhz cycle or 4.9 ns. additional resolution and lowe r final output jitter is provided by a de-jittering apll that reduces the 4.9 ns pk-pk jitter from the digita l down to 500 ps pk-pk and 60 ps rms as typical final outputs measured broadband (from 10 hz to 1 ghz).
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 20 www.semtech.com this arrangement combines the advantages of the flexibility and repeatability of a dpll with the low jitter of an apll. the dplls in the ACS8522BT are uniquely very programmable for all pll parameters of bandwidth (from 0.1 hz up to 70 hz), damping factor (from 1.2 to 20), frequency acceptance and output range (from 0 to 80 ppm, typically 9.2 ppm), input frequency (12 common sonet/sdh spot frequencies) and input-to-output phase offset (in 6 ps steps up to 200 ns). there is no requirement to understand th e loop filter equations or detailed gain parameters since all high level factors such as overall bandwidth can be set directly via registers in the microprocessor interface. no external critical components are required for either the internal dplls or aplls, providing another key advantage over traditional discrete designs. the t4 dpll is similar in structure to the t0 dpll, but since the t4 is only providing a clock synthesis and input to output frequency translation function, with no defined requirement for jitter attenuation or input phase jump absorption, then its bandwidth is limited to the high end and the t4 does not incorporate many of the phase build- out and adjustment facilities of the t0 dpll. to dpll main features ? two programmable dpll bandwidth controls (locked and acquisition bandwidth), each with 10 steps from 0.1 hz to 70 hz ? programmable damping factor: for optional faster locking and peaking control. factors = 1.2, 2.5, 5, 10 or 20 ? multiple phase lock detectors ? input to output phase offset adjustment (master/slave), 200 ns, 6 ps resolution step size ? pbo phase offset on source switching - disturbance down to 5 ns ? multi-cycle phase detection and locking, programmable up to 8192 ui - improves jitter tolerance in direct lock mode ? holdover frequency averaging with a choice of: average times: 8 minutes or 110 minutes. value can also be read out. ? multiple e1 and ds1 outputs supported ? low jitter mfrsync (2 khz) and frsync (8 khz) outputs. t4 dpll main features ? single programmable dpll bandwidth control: 18 hz, 35 hz or 70 hz ? programmable damping fact or: for optional faster locking and peaking control. factors = 1.2, 2.5, 5, 10 or 20 ? multiple phase lock detectors ? multi-cycle phase detection and locking, programmable up to 8192 ui - improves jitter tolerance in direct lock mode ? ds3/e3 support (44.736 mhz / 34.368 mhz) at same time as oc-n rates from t0 dpll ? low jitter e1/ds1 options at same time as oc-n rates from t0 dpll ? frequencies of n x e1/ds1 including 16 and 12 x e1, and 16 and 24 x ds1 supported ? low jitter mfrsync (2 khz) and frsync (8 khz) outputs ? can use the t4 dpll as an independent frsync dpll ? can use the phase detector in t4 dpll to measure the input phase difference between two inputs. the structure of the t0 and t4 plls are shown later in figure 10 in the section on output clock ports. that section also details how the dplls and particular output frequencies are configured. th e following sections detail some component parts of the dpll. to dpll automatic bandwidth controls in automatic bandwidth selection mode (reg. 3b), the t0 dpll bandwidth setting is se lected automatically from the acquisition bandwidt h or locked bandwidth configurations programmed in cnfg_t0_dpll_acq_bw reg. 69 and cnfg_t0_dpll_locked_bw reg. 67 respectively. if this mode is not selected, the dpll acquires and locks using only the bandwidth set by reg. 67. phase detectors a phase and frequency detector is used to compare input and feedback clocks. this operates at input frequencies up to 77.76 mhz. the whole dpll can operate at spot frequencies from 2 khz up to 77.76 mhz. a common arrangement however is to use lock8k mode (see bit 6 of reg. 22, 23, 27 and 28) where all input frequencies are divided down to 8 khz internally. marginally better mtie figures may be possible in dire ct lock mode due to more regular phase updates.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 21 www.semtech.com a patented multi-phase detector is used in order to give an infinitesimally small inpu t phase resolution combined with large jitter tolerance. the following phase detectors are used: ? phase and frequency detector (360 or 180 range) ? an early/late phase detector for fine resolution ? a multi-cycle phase detector for large input jitter tolerance (up to 8191 ui), which captures and remembers phase differences of many cycles between input and feedback clocks. the phase detectors can be configured to be immune to occasional missing input clock pulses by using nearest edge detection (180 capture) or the normal 360 phase capture range which gives frequency locking. the device will automatically switch to nearest edge locking when the multi-ui phase detector is not enabled and the other phase detectors have detected that phase lock has been achieved. it is possible to disable th e selection of nearest edge locking via reg. 03 bit 6 set to 1. in this setting, frequency locking will always be enabled. the balance between the first two types of phase detector employed can be adjusted vi a registers 6a to 6d. the default settings should be sufficient for all modes. adjustment of these settings affects only small signal overshoot and bandwidth. the multi-cycle phase detector is enabled via reg. 74, bit 6 set to 1 and the range is set in exponentially increasing steps from 1 ui, 3 ui, 7 ui, 15 ui ? up to 8191 ui via reg. 74, bits [3:0]. when this detector is enabled it keeps a track of the correct phase position over many cycles of phase difference to give excellent jitter tolerance. this provides an alternative to switching to lock8k mode as a method of achieving high jitter tolerance. an additional control (reg. 7 4 bit 5) enables the multi- phase detector value to be used in the final phase value as part of the dpll loop. when enabled by setting high , the multi cycle phase value will be used in the loop and gives faster pull in (but more overshoot). the characteristics of the loop will be similar to lock8k mode where again large input phase differences contribute to the loop dynamics. setting the bit low only uses a max figure of 360 degrees in the loop and will give slower pull- in but gives less overshoot. the final phase position that the loop has to pull in to is still tracked and remembered by the multi-cycle phase detector in either case. phase lock/loss detection phase lock/loss detection is handled in several ways. phase loss can be triggered from: ? the fine phase lock detector, which measures the phase between input and feedback clock ? the coarse phase lock detector, which monitors whole cycle slips ? detection that the dpll is at min. or max. frequency ? detection of no activity on the input. each of these sources of phase loss indication is individually enabled via register bits (see reg. 73, 74 and 4d). phase lock or lost is used to determine whether to switch to nearest edge locking and whether to use acquisition or locked band width settings for the dpll. acquisition bandwidth is used for faster pull-in from an unlocked state. the coarse phase lock detector detects phase differences of n cycles between input and feedback clocks, where n is set by reg. 74, bits 3:0; the same register that is used for the coarse phase detector range, since these functions go hand in hand. this detector may be used in the case where it is required that a phase loss indication is not given for reasonable amounts of input jitter and so the fine phase loss detector is disabled and the coarse detector is used instead. damping factor programmability the dpll damping factor is set by default to provide a maximum wander gain peak of around 0.1 db. many of the specifications (e.g. gr-1244-core, g.812 and g.813) specify a wander transfer gain of less than 0.2 db. gr-253 specifies jitter (not wa nder) transfer of less than 0.1 db. to accommodate the required levels of transfer gain, the ACS8522BT provides a choice of damping factors, with more choice given as the bandwidth setting increases into the frequency regions classified as jitter. table 5 shows which damping factors are avai lable for selection at the different bandwidth settings, and what the corresponding jitter transfer approximate gain peak will be.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 22 www.semtech.com local oscillator clock the master system clock on the ACS8522BT should be provided by an external cl ock oscillator of frequency 12.800 mhz. the clock specification is important for meeting the itu/etsi and telcordia performance requirements for holdover mode. itu and etsi specifications permit a combin ed drift characteristic, at constant temperature, of all non-temperature-related parameters, of up to 10 ppb per day. the same specifications allow a drift of 1 ppm over a temperature range of 0 to +70c. telcordia specifications are so mewhat tighter, requiring a non-temperature-related drift of less than 40 ppb per day and a drift of 280 ppb over the temperature range 0 to +50c. please contact semtech for information on crystal oscillator suppliers crystal frequency calibration the absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the ic. this allows for calibration and compensation of any crystal frequency variation away from its nominal value. 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8-bit register locations. the setting of the cnfg_nominal_frequency register allows for this adjustment. an increa se in the register value increases the output frequencies by 0.0196229 ppm for each lsb step. note...the default register value (in decimal) = 39321 (9999 hex) = 0 ppm offset. the minimum to maximum offset range of the register is 0 to 65535 dec, giving an adjustment range of -771 ppm to +514 ppm of the output frequencies, in 0.0196229 ppm steps. example: if the crystal was oscillating at 12.800 mhz + 5 ppm, then the calibration value in th e register to give a - 5 ppm adjustment in output freque ncies to compensate for the crystal inaccuracy, would be: 39321 - (5 / 0.0196229) = 39066 (dec) = 989a (hex). output wander wander and jitter present on the output clocks are dependent on: ? the magnitudes of wander and jitter on the selected input reference clock (in locked mode) ? the internal wander and jitt er transfer characteristic (in locked mode) ? the jitter on the local oscillator clock ? the wander on the local oscillator clock (in holdover mode). table 5 available damping factors for different dpll bandwidths, and associat ed jitter peak values bandwidth reg. 6b [2:0] damping factor selected gain peak/ db 0.1 hz to 4 hz 1, 2, 3, 4, 5 5 0.1 8 hz 1 2.5 0.2 2, 3, 4, 5 5 0.1 18 hz 1 1.2 0.4 22.50.2 3, 4, 5 5 0.1 35 hz 1 1.2 0.4 22.50.2 350.1 4, 5 10 0.06 70 hz 1 1.2 0.4 22.50.2 350.1 4100.06 5200.03 table 6 itu and etsi specification parameter value tolerance 4.6 ppm over 20 year lifetime drift (frequency drift over supply voltage range of +2.7 v to +3.3 v) 0.05 ppm/15 seconds @ constant temp. 0.01 ppm/day @ constant temp. 1 ppm over temp. range 0 to +70c table 7 telcordia gr-1244 core specification parameter value tolerance 4.6 ppm over 20 year lifetime drift (frequency drift over supply voltage range of +2.7 v to +3.3 v) 0.05 ppm/15 seconds @ constant temp. 0.04 ppm/15 seconds @ constant temp. 0.28 ppm/over temp. range 0 to +50c
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 23 www.semtech.com wander and jitter are treated in different ways to reflect their differing impacts on network design. jitter is always strongly attenuated, whilst wander attenuation can be varied to suit the applicatio n and operating state. wander and jitter attenuation is performed using a digital phase locked loop (dpll) with a programmable bandwidth. this gives a transfer characteristic of a low pass filter, with a programmable pole. it is so metimes necessary to change the filter dynamics to suit particular circumstances - one example being when locking to a new source, the filter can be opened up to reduce locking time and can then be tightened again to remove wander. a change between different bandwidths for lock ing and for acquisition is handled automatically within the ACS8522BT. there may be a phase shift across the ACS8522BT between the selected input reference source and the output clock over time, ma inly caused by frequency wander in the external oscilla tor module. higher stability xos will give better performance for mtie. the oscillator becomes more critical at dpll bandwidth near to or below 0.1 hz since the rate of change of the dpll may be slow compared to the rate of change of the oscillator frequency. shielding of the ocxo or tcxo can further slow down the rate of change of temperature and hence frequency, thus improving output wander performance. the phase shift may vary over time but will be constrained to lie within specified limits. the phase shift is characterized using two parameters, mtie (maximum time interval error) and tdev (time deviation) which, although being specified in all relevant specifications, differ in acceptable limits in each one. typical measurements for the ACS8522BT are shown in figure 5 , for locked mode operation. figure 6 shows a typical measurement of phase error accumulation in holdover mode operation. the required performance for phase variation during holdover is specified in several ways and depends on the relevant specification (see references and associated documents ), for example: 1. etsi ets-300 462-5, section 9.1, requires that the short-term phase error during switchover (i.e. locked to holdover to locked) be limited to an accumulation rate no greater than 0.05 ppm during a 15 second interval. 2. etsi ets-300 462-5, section 9.2, requires that the long-term phase error in the holdover mode should not exceed: {(a1 + a2)s + 0.5bs 2 + c} where a1 = 50 ns/s (allowance fo r initial frequency offset) a2 = 2000 ns/s (allowance for temperature variation) b = 1.16x10 -4 ns/s 2 (allowance for ageing) c = 120 ns (allowance for entry into holdover mode). s = elapsed time (s) after loss of external ref. input 3. ansi tin1.101-1999, section 8.2.2, requires that the phase variation be limited so that no more than 255 slips (of 125 s each) occur during the first day of holdover. this requires a frequency accuracy better than: ((24x60x60)+(255x125s))/( 24x60x60) = 0.37 ppm temperature variation is not restricted, except to within the normal bounds of 0c to 50c. 4. telcordia gr-1244-core, section 5.2, shows that an initial frequency offset of 50 ppb is permitted on entering holdover, whilst a drift over temperature of 280 ppb is allowed; an allowance of 40 ppb is permitted for all other effects. 5. itu g.822, section 2.6, requires that the slip rate during category (b) operation (interpreted as being applicable to holdover mode operation) be limited to less than 30 slips (of 125 s each) per hour. ((60 x 60) + (30 x 125 s))/(60 x 60)) = 1.042 ppm
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 24 www.semtech.com figure 5 maximum time interval error an d time deviation of t0 pll output port figure 6 phase error accumulation of t0 pll output port in holdover mode f8530d_027mtietdevcombf6_01 mtie for g.813 option 1, constant temperature wander limit tdev for g.813 option 1, constant temperature wander limit 10000000 1000000 100000 10000 1000 100 1000 10000 100000 observation interval (s) phase error (ns) permitted phase error limit typical measurement, 25c constant temperature
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 25 www.semtech.com jitter and wander transfer the ACS8522BT has a programmable jitter and wander transfer characterist ic. this is set by the dpll bandwidth. the -3 db jitter transfer attenuation point can be set in the range from 0.1 hz to 70 hz in 10 steps. the wander and jitter transfer characteristic is shown in figure 7 . wander on the local oscillator clock will not have a significant effect on the output clock whilst in locked mode, provided that the dpll bandwidth is set high enough so that the dpll can compensate quickl y enough for any frequency changes in the crystal. in free-run or holdover mode , wander on the crystal is more significant. variation in crystal temperature or supply voltage and ageing cause drifts in operating frequency. these effects must be limited by careful selection of a suitable component for the local oscillator, as specified in the section see local oscillator clock . phase build-out phase build-out (pbo) is the function to minimize phase transients on the output sec clock during input reference switching. if the currently selected input reference clock source is lost (due to a short interruption, out of frequency detection, or complete loss of reference) the second, next highest priority reference source will be selected, and a pbo event triggered. itu-t g.813 states that the maximum allowable short- term phase transient response , resulting from a switch from one clock source to another, with holdover mode entered in between, should be a maximum of 1 s over a 15 second interval. the maximum phase transient or jump should be less than 120 ns at a rate of change of less than 7.5 ppm and the holdover performance should be better than 0.05 ppm. the ACS8522BT performance is well within this requirement. the typical phase disturbance on clock reference source switching will be less than 5 ns on the ACS8522BT. when a pbo event is triggered, the device enters a temporary holdover state. when in this temporary state, the phase of the input reference is measured, relative to the output. the device then automatically accounts for any measured phase difference and adds the appropriate phase offset into the dpll to compensate. following a pbo event, whatever the phase difference on change of input, the output phase transi ent is minimized to be no greater than 5 ns. on the ACS8522BT, pbo can be enabled, disabled or frozen using the serial interfac e. by default, it is enabled. when pbo is enabled, pbo can also be frozen (at the current offset setting). the device will then ignore any further pbo events occurring on any subsequent reference switch, and maintain the current phase offset. if pbo is disabled figure 7 sample of wander and jitter measured transfer characteristics
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 26 www.semtech.com while the device is in the locked mode, there may be a phase shift on the output sec clocks as the dpll locks back to 0 degrees phase error. the rate of phase shift will depend on the programmed bandwidth. enabling pbo whilst in the locked stated will also trigger a pbo event. pbo phase offset in order to minimize the systematic (average) phase error for pbo, a pbo phase offset can be programmed in 0.101 ns steps in the cnfg_pbo_phase_offset register, reg.72. the range of the programmable pbo phase offset is restricted to 1.4 ns. this can be used to eliminate an accumulation of phase shifts in one direction. input-to-output phase adjustment when pbo is off (including auto-pbo on phase transients), such that the system always tries to align the outputs to the inputs at the 0 position, there is a mechanism provided in the ACS8522BT for precise fine tuning of the output phase position with respect to the input. this can be used to compensate for circuit and board wiring delays. the output phase can be adjusted in 6 ps steps up to 200 ns in a positive or negative direction. the phase adjustment actually changes the phase position of the feedback clock so that the dpll adjusts the output clock phases to compensate. the rate of change of phase is therefore related to the dpll bandwidth. for the dpll to track large instant changes in phase, either lock8k mode should be on, or the coarse phase detector should be enabled. register cnfg_phase_offset at reg. 70 and 71 controls the output phase, which is only used when pbo is off (reg. 48, bit 2 = 0 and reg. 76, bit 4 = 0). input wander and jitter tolerance the ACS8522BT is compliant to the requirements of all relevant standards, principally itu recommendation g.825, ansi ds1.101-1999, telcordia gr1244, gr253, g812, g813 and ets 300 462-5 (1996). all reference clock inputs have a tight frequency tolerance but a generous jitter toleranc e. pull-in, hold-in and pull-out ranges are specified in table 8 . minimum jitter tolerance masks are specified in figure 8 and figure 9 and table 8 and table 10 respectively. the ACS8522BT will tolerate wander and jitter components greater than those shown in figure 8 and figure 9 , up to a limit determined by a combination of the apparent long-term frequency offset caused by wander and the eye-closure caused by jitter (the input source will be rejected if the offset pushes the frequency outside the hold-in range for long enough to be detected, whilst the signal will also be rejected if the eye closes sufficiently to affect the signal purity). either the lock8k mode, or one of the extended phase capture ranges should be engaged for high jitter tolerance according to these masks. all reference clock ports are monitored for quality, including frequency offset and general activity. single short-term interruptions in selected reference clocks may not cause re- arrangements, wh ilst longer interruptions, or multiple, short-term inte rruptions, will cause re- arrangements, as will frequency offsets which are sufficiently large or sufficiently long to cause loss-of-lock in the phase-locked loop. the failed reference source will be removed from the priority table and declared as unserviceable, until its pe rceived quality has been restored to an acceptable level.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 27 www.semtech.com notes: (i) the frequency acceptance and generation range will be 4.6 ppm around the required fr equency when the external crysta l frequency accuracy is within a tolerance of 4.6 ppm. (ii) the fundamental acceptance range and generation range is 9.2 ppm with an exact external crys tal frequency of 12.800 mhz. t his is the default dpll range, the range is also pr ogrammable from 0 to 80 ppm in 0.08 ppm steps. figure 8 minimum input jitter tolerance (oc-3/stm-1) table 8 input reference source jitter tolerance jitter tolerance frequency monitor acceptance range frequency acceptance range (pull-in) frequency acceptance range (hold-in) frequency acceptance range (pull-out) g.703 16.6 ppm 4.6 ppm (see note (i)) 9.2 ppm (see note (ii)) 4.6 ppm (see note (i)) 9.2 ppm (see note (ii)) 4.6 ppm (see note (i)) 9.2 ppm (see note (ii)) g.783 g.823 gr-1244-core f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 a0 a1 a2 a3 a4 jitter and wander frequency (log scale) f8530_003minipjittoloc3stm1_02 note...for inputs supporting g.783 compliant sources.) table 9 amplitude and frequency values for jitter tolerance (oc-3/stm-1) stm level peak to peak amplitude (unit interval) frequency (hz) a0 a1 a2 a3 a4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 stm-1 2800 311 39 1.5 0.15 12 u 178 u 1.6 m 15.6 m 0.125 19.3 500 6.5 k 65 k 1.3
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 28 www.semtech.com figure 9 minimum input jitter tolerance (ds1/e1) using the dplls for accurate frequency and phase reporting the frequency monitors in the ACS8522BT perform frequency monitoring with a programmable acceptable limit of up to 60.96 ppm. the resolution of the measurement is 3.8 ppm and the measured frequency can be read back from reg. 4c, with channel selection at reg. 4b. for more accurate measurement of both frequency and phase, the t0 and t4 dplls and their phase detectors, can be used to monitor both input frequency and phase. the t0 dpll is always monitoring the currently locked to source, but if the t4 path is not used then the t4 dpll can be used as a roving phase and frequency meter. via software control it could be switched to monitor each input in turn and both the phase and frequency can be reported with a very fine resolution. the registers sts_current_dpll_frequency (reg. 0c, 0d and 07) report the frequency of either the t0 or t4 dpll with respect to the external crystal xo frequency (after calibration via reg. 3c, reg. 3d if used). the selection of t4 or t0 dpll reporting is made via reg. 4b, bit 4. the value is a 19-bit signed number with one lsb representing 0.0003068 ppm (range of 80 ppm). this value is actually the integral path value in the dpll, and as such corresponds to an averaged measurement of the input frequency, with an averaging time inversely proportional to the dpll bandwidth setting. reading this regularly can show how the currently locked source is varying in value e.g. due to frequency wander on its input. the input phase, as seen at the dpll phase detector, can be read back from register sts_current_phase , reg. 77 and 78. t0 or t4 dpll phase detector reporting is again controlled by reg. 4b, bit 4. one lsb corresponds to approximately 0.7 degrees phase difference. for the t0 dpll this will be reporting the phase difference between the input and the internal feedback clock. the phase result is internally averaged or filtered with a -3 db attenuation point at approximately 100 hz. for low dpll bandwidths, 0.1 hz for example, this measured phase information from the t0 dpll gives input phase wander in the frequency band from for example 0.1 hz to 100 hz. this could be used to give a crude input mtie measurement up to an observation period of approximately 1000 seconds using external software. in addition, the t4 dpll phase detector can be used to make a phase measurement between two inputs. reg. 65, bit 7 is used to switch one input to the t4 phase detector over to the current t0 input. a1 a2 jitter and wander frequency (log scale) peak-to-peak jitter and wander amplitude (log scale) f1 f2 f3 f4 f8530d_004minipjittolds1e1_02 table 10 amplitude and frequency values for jitter tolerance (ds1/e1) type spec. amplitude (ui pk-pk) frequency (hz) a1 a2 f1 f2 f3 f4 ds1 gr-1244-core 5 0.1 10 500 8 k 40 k e1 itu g.823 1.5 0.2 20 2.4 k 18 k 100
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 29 www.semtech.com the other phase detector input remains connected to the selected t4 input source, th e selected source can be forced via reg. 35, bits 3:0, or changed via the t4 priority (reg. 19 to 1c, when reg. 4b, bit 4 = 1). consequently the phase detector from the t4 dpll could be used to measure the phase difference between the currently selected source and the stand-by source, or it could be used to measure the phase wander of all stand- by sources with respect to th e current source by selecting each input in sequence. an mtie and tdev calculation could be made for each input via external processing. mfrsync and frsync alignment-sync2k the sync2k input will normally be a 2 khz frequency and only its falling edge is used. it can however be at a frequencies of 4 khz or 8 khz without any change to the register setups. only alig nment of the 8 khz will be achieved in this case. safe sampling of the sync2k input is achieved by using the currently selected clock reference source to do the input sampling. this is based on the principle that frsync alignment is being used on a slave device that is locked to the clock reference of a master device that is also providing the 2 khz sync2k input. phase build-out mode should be off (reg. 48, bit 2 = 0). the 2 khz mfrsync output from the master device has its falling edge aligned with the falling edge of the other output clocks, hence the sync2k input is normally sampled on the rising edge of the current input reference clock, in order to provide the most margin. some modification of the expected timing of the sync2k with respect to the reference clock can be achieved via reg. 7b, bits [1:0]. this allows for the sync2k input to arrive either half a reference clock cycle early or up to one and a half cycle late, hence allowing a safe sampling margin to be maintained. a different sampling resolution is used depending on the input reference frequency an d the setting of reg. 7b, cnfg_sync_phase, bit 6 indep_frsync/mfrsync . with this bit low , the sync2k input sampling has a 6.48 mhz resolution, this being the preferred reference frequency to lock to from the master, in conjunction with the sync2k 2 khz, since it gives the most timing margin on the sampling and aligns all of the higher rate oc-3 derived clocks. when bit 6 is high the sync2k can have a sampling resolution of either 19.44 mhz (when the current locked to reference is 19.44 mhz) or 38.88 mhz (all other frequencies). this would allow for instance a 19.44 mhz and 2 khz pair to be used for slave synchronization or for line card synchronization. reg. 7b bit 7, indep_frsync/mfrsync controls whether the 2 khz mfrsync and 8 khz frsync outputs keep their precise alignment with the other output clocks. when indep_frsync/mfrsync reg. 7b bit 7 is low the frsyncs and the other higher rate clocks are not independent and their alignment on the falling 8khz edge is maintained. this means that when bit sync_oc-n_rates is high , the oc-n rate dividers and clocks are also synchronized by the sync2k input. on a change of phase position of the sync2k, this could result in a shift in phase of the 6.48 mhz output clock when a 19.44 mhz precision is used for the sync2k input. to avoid disturbing any of the output clocks and only align the mfrsync and frsync outputs, at the chosen level of precision, then independent frame sync mode can be used (reg. 7b, bit 7 = 1). edge alignment of the frsync output with other clocks outputs may then change depending on the sync2k sampling precision used. for example with a 19.44 mhz reference input clock and reg. 7b, bits 6 & 7 both high (independent mode and sync oc-n rates), then the frsync output will still align with the 19.44 mhz output but not with the 6.48 mhz output clock. the frsync and mfrsync outp uts always come from the t0 dpll path. 2khz and 8khz outputs can also be produced at the o1 to o4 outputs. these can come from either the t0 dpll or from the t4 dpll, controlled by reg. 7a, bit 7. if required, this allows the t4 dpll to be used as a separate pll for the frsync and mfrsync path with a 2khz input and 2khz and 8khz frame sync outputs. output clock ports the device supports a set of main output clocks, o1 to o4 and a pair of secondary sync outputs, frsync and mfrsync. the four main output clocks are independent of each other and are individu ally selectable. the two secondary output clocks, frsync and mfrsync, are derived from the t0 path only. the frequencies of the main output clocks are sele ctable from a range of pre- defined spot frequencies as defined in table 11 . output technologies are ttl/cmos for all outputs except o1 which can be pecl or lvds.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 30 www.semtech.com pecl/lvds output port selection the choice of pecl or lvds compatibility for output o1 is programmed via the cnfg_differential_outputs register, reg. 3a. output frequency selection and configuration the output frequency of outputs o1 to o4 is controlled by a number of interdependent parameters. these parameters control the selections within the various blocks shown in figure 10 . the ACS8522BT contains two main dpll/apll paths, t0 and t4. whilst they are largely independent, there are a number of ways in which these two structures can interact. figure 10 is an expansion of figure 1 showing the pll paths in more detail. t0 dpll and aplls the t0 dpll always produces 77.76 mhz regardless of either the reference frequency (frequency at the input pin of the device) or the locking frequency (frequency at the input of the dpll phase and frequency detector (pfd)). the input reference is either passed directly to the pfd or via a pre-divider (not shown) to produce the reference input. the feedback 77.76 mhz is either divided or synthesized to generate the locking frequency. digital frequency synthesis (dfs) is a technique for generating an output frequency using a higher frequency system clock (204.8 mhz in the case of the 77.76 mhz synthesis). however, the edges of the output clock are not ideally placed in time, since all edges of the output clock will be aligned to the active edge of the system clock. this will mean that the generated clock will inherently have jitter on it equivalent to on e period of the system clock. the t0 77m forward dfs block uses dfs clocked by the 204.8 mhz system clock to synthesize the 77.76 mhz and, therefore, has an inhere nt 4.9 ns of pk-pk jitter. there is an option to use an apll, the t0 feedback apll, to filter out this jitter before the 77.76 mhz is used to generate the feedback locking frequency in the t0 feedback dfs block. this analog feedback option allows a lower jitter (<1 ns) feedback signal to give maximum performance. the digital feedback option is present so that when the output path is switched to digital feedback the two paths remain synchronized. the t0 77m forward dfs block is also the block that handles phase build-out and any phase offset programmed into the device. hence, the t0 77m forward dfs and the t0 77m output dfs blocks are locked in frequency but may be offset in phase. the t0 77m output dfs block also uses the 204.8 mhz system clock and always generates 77.76 mhz for the output clocks (with inherent 4.9 ns of jitter). this is fed to another dfs block and to the t0 output apll. the low frequency t0 lf output dfs block is used to produce three frequencies; two of them, digital1 and digital2, are available for selection to be produced at outputs o1 to o4, and the third frequency ca n produce multiple e1/ds1 rates via the filtering aplls. the input clock to the t0 lf output dfs block is either 77.76 mhz from the t0 output apll (post jitter filtering) or 77.76 mhz direct from the t0 77m output dfs. utilizing th e clock from the t0 output apll will result in lower jitt er outputs from the t0 lf output dfs block. however, when the input to the t0 apll is taken from the t0 lf output dfs block, the input to that block comes directly from the t0 77m output dfs block so that a ?loop? is not created. the t0 output apll is for multiplying and filtering. the input to the t0 output apll can be either 77.76 mhz from the t0 77m output dfs block or an alternative frequency from the t0 lf output dfs block (offering 77.76 mhz, 12e1, 16e1, 24ds1 or 16ds1). the frequency from the t0 output apll is four time s its input frequency i.e. 311.04 mhz when used with a 77.76 mhz input. the t0 output apll is subsequently divided by 1, 2, 4, 6, 8, 12, 16 and 48 and these are available at the o1 to o4 outputs. t0 ethernet modes the device includes an ethernet clock generator synchronized to the 77.76 mhz output dfs of the t0 path. the aplls and clock dividers associated with this path are controlled via the cnfg_output_frequency register (reg 20). by default, the ethernet clock path is enabled and can be used to generate frequencies of 25 mhz, 50 mhz, 62,5 mhz or 125 mhz, which ar e available for output via 01 to o4 selected via reg 60 to reg 62. for applications that do not require ethernet frequencies, to conserve power it is recommended that the ethernet clock path is disabled.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 31 www.semtech.com t4 dpll & apll the t4 path is much simpler than the t0 path. this path offers no phase build-out or phase offset. the t4 input can be used to either lock to a reference clock input independent of the t0 path, or lock to the t0 path. unlike the t0 path, the t4 forward dfs block does not always generate 77.76 mhz. the possi ble frequencies are listed in the table. similar to the t0 path, the output of the t4 forward dfs block is generated using dfs clocked by the 204.8 mhz system clock and will have an inherent jitter of 4.9 ns. the t4 feedback dfs also has the facility to be able to use the post t4 apll (jitter-filtered) clock to generate the feedback locking frequency. again, this will give the maximum performance by usin g a low jitter feedback. figure 10 pll block diagram the t4 output apll is also fo r multiplying and filtering. the input to the block can come from the t4 forward dfs block or from the t0 path. the input to the t4 output apll can be programmed to be one of the following: (a) output from the t4 forward dfs block (12e1, 24ds1, 16e1, 16ds1, e3, ds3, oc-n), (b) 12e1 from t0, (c) 16e1 from t0, (d) 24ds1 from t0, (e) 16ds1 from t0. the frequency generated from the t4 output apll block is four times its input frequency i.e. 311.04 mhz when used with a 77.76 mhz input. the t4 output apll is subsequently divided by 2, 4, 8, 12, 16, 48 and 64 and these are available at the o1 to o4 outputs. the outputs o1 to o4 are driven from either the t4 or the t0 path. the frsync and mfrsync outputs are always generated from the t0 path. reg.7a bit 7 selects whether the source of the 2 khz and 8 khz outputs available from o1 to o4 is derived from either the t0 or the t4 paths.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 32 www.semtech.com output frequency configuration steps the output frequency select ion is performed in the following steps: 1. does the application require the use of the t4 path as an independent pll path or not. if not, then the t4 path can be utilized to produce extra frequencies locked to the t0 path. 2. refer to table 13 to choose a set of output frequencies - one for each path. only one set of frequencies can be genera ted simultaneously from each path. 3. refer to table 13 to determine the required apll frequency to support the frequency set. 4. refer to table 14 and table 15 to determine the mode in which the t0 and t4 paths are to be configured, considering the output jitter level. 5. refer to table 16 and the column headings in table 13 to select the appropriate frequency from either of the aplls on each output as required. note...1.544 mhz/2.048 mhz are shown for sonet/sdh respectively. pin sonsdhb controls default, when high sonet is default. table 11 output reference source selection table port name output port technology frequencies supported o1 lvds/pecl (lvds default) frequency selection as per table 12 and table 16 o2 ttl/cmos o3 ttl/cmos o4 ttl/cmos frsync ttl/cmos frsync, 8 khz programmable pulse width and polarity, see reg. 7a. mfrsync ttl/cmos mfrsync, 2 khz programmable pulse width and polarity, see reg. 7a. table 12 output frequency selection frequency (mhz, unless stated otherwise) t0 dpll mo de t4 dpll mode t4 apll input mux jitter level (typ) rms (ps) pk-pk (ns) 2 khz 77.76 mhz analog - - 60 0.6 2 khz any digital feedback mode - - 1400 5 8 khz 77.76 mhz analog - - 60 0.6 8 khz any digital feedback mode - - 1400 5 1.536 (not o4) - 12e1 mode select t4 dpll 500 2.3 1.536 (not o4) - - select t0 dpll 12e1 250 1.5 1.544 (not o4) - 16ds1 mode select t4 dpll 200 1.2 1.544 (not o4) - - select t0 dpll 16ds1 150 1.0 1.544 via digital1, or digital2 (n ot o1) 77.76 mhz analog - - 3800 13
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 33 www.semtech.com 1.544 via digital1, or digital2 (not o1) any digital feedback mode - - 3800 18 2.048 - 12e1 mode select t4 dpll 500 2.3 2.048 - - select t0 dpll 12e1 250 1.5 2.048 (not o4) - 16e1 mode select t4 dpll 400 2.0 2.048 (not o4) - - select t0 dpll 16e1 220 1.2 2.048 (not o1) 12e1 mode - - 900 4.5 2.048 via digital1, or digital2 (n ot o1) 77.76 mhz analog - - 3800 13 2.048 via digital1, or digital2 (not o1) any digital feedback mode - - 3800 18 2.059 - 16ds1 mode select t4 dpll 200 1.2 2.059 - - select t0 dpll 16ds1 150 1.0 2.059 (not o1) 16ds1 mode - - 760 2.6 2.316 (not o4) - 24ds1 mode select t4 dpll 110 0.75 2.316 (not o4) - - select t0 dpll 24ds1 110 0.75 2.731 - 16e1 mode select t4 dpll 400 1.5 2.731 - - select t0 dpll 16e1 220 1.2 2.731 (not o1) 16e1 mode - - 250 1.6 2.796 (not o4) - ds3 mode select t4 dpll 110 1.0 3.088 - 24ds1 mode select t4 dpll 110 0.75 3.088 - - select t0 dpll 24ds1 110 0.75 3.088 (not o1) 24ds1 mode - - 110 0.75 3.088 via digital1, or digital2 (n ot o1) 77.76 mhz analog - - 3800 13 3.088 via digital1, or digital2 (not o1) any digital feedback mode - - 3800 18 3.728 - ds3 mode select t4 dpll 110 1.0 4.096 via digital1, or digital2 (n ot o1) 77.76 mhz analog - - 3800 13 4.096 via digital1, or digital2 (not o1) any digital feedback mode - - 3800 18 4.296 (not o4) - e3 mode select t4 dpll 120 1.0 4.86 (not o4) - 77.76 mhz mode select t4 dpll 60 0.6 table 12 output frequency selection (cont...) frequency (mhz, unless stated otherwise) t0 dpll mo de t4 dpll mode t4 apll input mux jitter level (typ) rms (ps) pk-pk (ns)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 34 www.semtech.com 5.728 - e3 mode select t4 dpll 120 1.0 6.144 12e1 mode - - 900 4.5 6.144 - 12e1 mode select t4 dpll 500 2.3 6.144 - - select t0 dpll 12e1 250 1.5 6.176 16ds1 mode - - 760 2.6 6.176 - 16ds1 mode select t4 dpll 200 1.2 6.176 - - select t0 dpll 16ds1 150 1.0 6.176 via digital1, or digital2 (n ot o1) 77.76 mhz analog - - 3800 13 6.176 via digital1, or digital2 (not o1) any digital feedback mode - - 3800 18 6.48 - 77.76 mhz mode select t4 dpll 60 0.6 6.48 (not o1) 77.76 mhz analog - - 60 0.6 6.48 (not o1) 77.76 mhz digital - - 60 0.6 8.192 12e1 mode - - 900 4.5 8.192 16e1 mode - - 250 1.6 8.192 - 16e1 mode select t4 dpll 400 2.0 8.192 - - select t0 dpll 16e1 220 1.2 8.192 via digital1, or digital2 (n ot o1) 77.76 mhz analog - - 3800 13 8.192 via digital1, or digital2 (not o1) any digital feedback mode - - 3800 18 8.235 16ds1 mode - - 760 2.6 9.264 24ds1 mode - - 110 0.75 9.264 - 24ds1 mode select t4 dpll 110 0.75 9.264 - - select t0 dpll 24ds1 110 0.75 10.923 16e1 mode - - 250 1.6 11.184 - ds3 mode select t4 dpll 110 1.0 12.288 12e1 mode - - 900 4.5 12.288 - 12e1 mode select t4 dpll 500 2.3 12.288 - - select t0 dpll 12e1 250 1.5 12.352 24ds1 mode - - 110 0.75 table 12 output frequency selection (cont...) frequency (mhz, unless stated otherwise) t0 dpll mo de t4 dpll mode t4 apll input mux jitter level (typ) rms (ps) pk-pk (ns)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 35 www.semtech.com 12.352 16ds1 mode - - 760 2.6 12.352 - 16ds1 mode select t4 dpll 200 1.2 12.352 - - select t0 dpll 16ds1 150 1.0 12.352 via digital1, or digital2 (not o1) 77.76 mhz analog - - 3800 13 12.352 via digital1, or digital2 (not o1) any digital feedback mode - - 3800 18 16.384 12e1 mode - - 900 4.5 16.384 16e1 mode - - 250 1.6 16.384 - 16e1 mode select t4 dpll 400 2.0 16.384 - - select t0 dpll 16e1 220 1.2 16.384 via digital1, or digital2 (n ot o1) 77.76 mhz analog - - 3800 13 16.384 via digital1, or digital2 (not o1) any digital feedback mode - - 3800 18 16.469 16ds1 mode - - 760 2.6 17.184 - e3 mode select t4 dpll 120 1.0 18.528 24ds1 mode - - 110 0.75 18.528 - 24ds1 mode select t4 dpll 110 0.75 18.528 - - select t0 dpll 24ds1 110 0.75 19.44 77.76 mhz analog - - 60 0.6 19.44 77.76 mhz digital - - 60 0.6 19.44 - 77.76mhz mode select t4 dpll 60 0.6 21.845 16e1 mode - - 250 1.6 22.368 - ds3 mode select t4 dpll 110 1.0 24.576 12e1 mode - - 900 4.5 24.576 - 12e1 mode select t4 dpll 500 2.3 24.576 - - select t0 dpll 12e1 250 1.5 24.704 24ds1 mode - - 110 0.75 24.704 16ds1 mode - - 760 2.6 24.704 - 16ds1 mode select t4 dpll 200 1.2 24.704 - - select t0 dpll 16ds1 150 1.0 table 12 output frequency selection (cont...) frequency (mhz, unless stated otherwise) t0 dpll mo de t4 dpll mode t4 apll input mux jitter level (typ) rms (ps) pk-pk (ns)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 36 www.semtech.com 25.0 77.76 mhz analog - - 90.2 0.76 25.0 77.76 mhz digital - - 83.5 0.65 25.92 77.76 mhz analog - - 60 0.6 25.92 77.76 mhz digital - - 60 0.6 32.768 16e1 mode - - 250 1.6 32.768 - 16e1 mode select t4 dpll 400 2.0 32.768 - - select t0 dpll 16e1 220 1.2 34.368 - e3 mode select t4 dpll 120 1.0 37.056 24ds1 mode - - 110 0.75 37.056 - 24ds1 mode select t4 dpll 110 0.75 37.056 - - select t0 dpll 24ds1 110 0.75 38.88 77.76 mhz analog - - 60 0.6 38.88 77.76 mhz digital - - 60 0.6 38.88 - 77.76 mhz mode select t4 dpll 60 0.6 44.736 - ds3 mode select t4 dpll 110 1.0 49.152 (o4 only) - 12e1 mode select t4 dpll 500 2.3 49.152 (o4 only) - - select t0 dpll 12e1 250 1.5 49.152 (o1 only) 12e1 mode - - 900 4.5 49.408 (o4 only) - 16ds1 mode select t4 dpll 200 1.2 49.408 (o4 only) - - select t0 dpll 16ds1 150 1.0 49.408 (o1 only) 16ds1 mode - - 760 2.6 50.0 77.76 mhz analog - - 76.9 0.73 50.0 77.76 mhz digital - - 61.6 0.6 51.84 77.76 mhz analog - - 60 0.6 51.84 77.76 mhz digital - - 60 0.6 62.5 77.76 mhz analog - - 68.2 0.56 62.5 77.76 mhz digital - - 70.0 0.58 65.536 (o4 only) - 16e1 mode select t4 dpll 400 2.0 65.536 (o4 only) - - select t0 dpll 16e1 220 1.2 table 12 output frequency selection (cont...) frequency (mhz, unless stated otherwise) t0 dpll mo de t4 dpll mode t4 apll input mux jitter level (typ) rms (ps) pk-pk (ns)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 37 www.semtech.com 65.536 (o1 only) 16e1 mode - - 250 1.6 68.736 - e3 mode select t4 dpll 120 1.0 74.112 (o4 only) - 24ds1 mode select t4 dpll 110 0.75 74.112 (o4 only) - - select t0 dpll 24ds1 110 0.75 74.112 (o1 only) 24ds1 mode - - 110 0.75 77.76 77.76 mhz analog - - 60 0.6 77.76 77.76 mhz digital - - 60 0.6 77.76 - 77.76 mhz mode select t4 dpll 60 0.6 89.472 (o4 only) - ds3 mode select t4 dpll 110 1.0 98.304 (o1 only) 12e1 mode - - 900 4.5 98.816 (o1 only) 16ds1 mode - - 760 2.6 125.0 77.76 mhz analog - - 76.8 0.57 125.0 77.76 mhz digital - - 66.42 0.53 131.07 (o1 only) 16e1 mode - - 250 1.6 137.47 (o4 only) - e3 mode select t4 dpll 120 1.0 148.22 (o1 only) 24ds1 mode - - 110 0.75 155.52 (o4 only) - 77.76 mhz mode select t4 dpll 60 0.6 155.52 (o1 only) 77.76 mhz analog - - 60 0.6 155.52 (o1 only) 77.76 mhz digital - - 60 0.6 311.04 (o1 only) 77.76 mhz analog - - 60 0.6 311.04 (o1 only) 77.76 mhz digital - - 60 0.6 table 12 output frequency selection (cont...) frequency (mhz, unless stated otherwise) t0 dpll mo de t4 dpll mode t4 apll input mux jitter level (typ) rms (ps) pk-pk (ns)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 38 www.semtech.com note...all frequencies in mhz table 13 frequency divider look-up apll frequency apll/2 apll/4 apll/6 apll/8 apll/12 apll/16 apll/48 apll/64 311.04 155.52 77.76 51.84 38.88 25.92 19.44 6.48 4.86 274.944 137.472 68.376 - 34.368 - 17.184 5.728 4.296 178.944 89.472 44.736 - 22.368 - 11.184 3.728 2.796 148.224 74.112 37.056 24,704 18.528 12.352 9.264 3.088 2.316 131.072 65.536 32.768 21.84533 16.384 10.92267 8.192 2.730667 2.048 98.816 49.408 24.704 16.46933 12.352 8.234667 6.176 2.058667 1.544 98.304 49.152 24.576 16.384 12.288 8.192 6.144 2.048 1.536
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 39 www.semtech.com table 14 t0 apll frequencies t0 apll frequency t0 mode t0 dpll frequency control register bits reg. 65 bits[2:0] output jitter level ns (pk-pk) 311.04 mhz normal (digital feedback) 000 <0.5 311.04 mhz normal (analog feedback) 001 <0.5 98.304 mhz 12e1 (digital feedback) 010 <2 131.072 mhz 16e1 (digital feedback) 011 <2 148.224 mhz 24ds1 (digital feedback) 100 <2 98.816 mhz 16ds1 (digital feedback) 101 <2 - do not use 110 - - do not use 111 - table 15 t4 apll frequencies t4 apll frequency t4 mode t4 forward dfs frequency (mhz) t4 dpll freq. control register bits reg. 64 bits [2:0] t4 apll for t0 enable register bit reg. 65 bit 6 t0 freq. to t4 apll register bits reg. 65 bits [5:4] output jitter level ns (pk-pk) 311.04 mhz squelched 77.76 000 0 xx <0.5 311.04 mhz normal 77.76 001 0 xx <0.5 98.304 mhz 12e1 24.576 010 0 xx <0.5 131.072 mhz 16e1 32.768 011 0 xx <0.5 148.224 mhz 24ds1 37.056 (2*18.528) 100 0 xx <0.5 98.816 mhz 16ds1 24.704 101 0 xx <0.5 274.944 mhz e3 68.736 (2*34.368) 110 0 xx <0.5 178.944 mhz ds3 44.736 111 0 xx <0.5 98.304 mhz t0-12e1 - xxx 1 00 <2 131.072 mhz t0-16e1 - xxx 1 01 <2 148.224 mhz t0-24ds1 - xxx 1 10 <2 98.816 mhz t0-16ds1 - xxx 1 11 <2
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 40 www.semtech.com table 16 o1 to o4 sonet output frequency selection output frequency for given value in register for each output port?s cnfg_output_frequency register value in register reg. 20[5] = 0 o1, reg. 62 bits [7:4] reg. 20[1] = 0 o2, reg. 60 bits [7:4] reg. 20[2] = 0 o3, reg. 61 bits [3:0] reg. 20[4] = 0 o4, reg. 62 bits [3:0] 0000 off off off off 0001 2 khz 2 khz 2 khz 2 khz 0010 8 khz 8 khz 8 khz 8 khz 0011 t0 apll/2 digital2 digital2 digital2 0100 digital1 digital1 digital1 digital1 0101 t0 apll/1 t0 apll/48 t0 apll/48 t0 apll/48 0110 t0 apll/16 t0 apll/16 t0 apll/16 t0 apll/16 0111 t0 apll/12 t0 apll/12 t0 apll/12 t0 apll/12 1000 t0 apll/8 t0 apll/8 t0 apll/8 t0 apll/8 1001 t0 apll/6 t0 apll/6 t0 apll/6 t0 apll/6 1010 t0 apll/4 t0 apll/4 t0 apll/4 t0 apll/4 1011 t4 apll/64 t4 apll/64 t4 apll/64 t4 apll/2 1100 t4 apll/48 t4 apll/48 t4 apll/48 t4 apll/48 1101 t4 apll/16 t4 apll/16 t4 apll/16 t4 apll/16 1110 t4 apll/8 t4 apll/8 t4 apll/8 t4 apll/8 1111 t4 apll/4 t4 apll/4 t4 apll/4 t4 apll/4 table 17 o1 to o4 ethernet output frequency selection output frequency for given value in register for each output port?s cnfg_output_frequency register value in register reg. 20[5] = 1 o1, reg. 62 bits [7:4] reg. 20[1] = 1 o2, reg. 60 bits [7:4] reg. 20[2] = 1 o3, reg. 61 bits [3:0] reg. 20[4] = 1 o4, reg. 62 bits [3:0] xx00 25mhz 25mhz 25mhz 25mhz xx01 50mhz 50mhz 50mhz 50mhz xx10 62.5 mhz 62.5 mhz 62.5 mhz 62.5 mhz xx11 125 mhz 125 mhz 125 mhz 125 mhz
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 41 www.semtech.com digital frequencies it can be seen in table 16 that frequencies listed as digital1 and digital2 can be se lected. digital1 is a single frequency selected from the range shown in table 18 . digital2 is another single frequency selected from the same range. the t0 lf output dfs block shown in the diagram and clocked either by the t0 77m output dfs block or via the t0 output apll, generates these two frequencies. the input clock frequency of the dfs is always 77.76 mhz and as such has a period of approximately 12 ns. the jitter generated on the digital outputs is relatively high, due to the fact that they do not pass through an apll for jitter filtering. the minimum level of jitter is when the t0 path is in analog feedback mode, when the pk-pk jitter will be approximately 12 ns (equivalent to a period of the dfs clock). the maximum jitter is generated when in digital feedback mode, when the total is approximately 17 ns. frsync, mfrsync, 2 khz and 8 khz clock outputs it can be seen from table 16 that frequencies listed as 2khz and 8khz can be select ed. whilst the frsync and mfrsync outputs are always supplied from the t0 path, the 2 khz and 8 khz options available from the o1 to o4 outputs are all supplied from either the t0 or t4 path (reg. 7a bit 7). the outputs can be clocks ( 50:50 mark-space) or pulses and can be inverted. when pulses are configured on the output, the pulse width will be one cycle of the output of o3 (o3 must be configured to generate at least 1544 khz to ensure that pulses are generated correctly). figure 11 shows the various options with the 8 khz controls in reg. 7a. there is an identical arrangement with reg. 7a bits [1:0] and the 2 khz/mfrsync outputs. outputs frsync and mfrsync can be disabled via reg. 63 bits [7:6]. figure 11 control of 8k options. table 18 digital frequency selections digital1 control reg.39 bits [5:4] digital1 sonet/ sdh reg. 38 bit5 digital1 freq. (mhz ) digital2 control reg. 39 bits[7:6] digital2 sonet/sdh reg.38 bit6 digital2 freq. (mhz) 00 0 2.048 00 0 2.048 01 0 4.096 01 0 4.096 10 0 8.192 10 0 8.192 11 0 16.384 11 0 16.384 00 1 1.544 00 1 1.544 01 1 3.088 01 1 3.088 10 1 6.176 10 1 6.176 11 1 12.352 11 1 12.352 f8522_016outputoptions8k_01 03 output frsync/8khz output frsync/8khz output a) clock non-inverted, reg.7a[3:2] = 00 b) pulse non-inverted, reg.7a[3:2] = 01 c) clock inverted, reg.7a[3:2] = 10 d) pulse inverted, reg.7a[3:2] = 11 frsync/8khz output frsync/8khz output 03 output 03 output 03 output
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 42 www.semtech.com power-on reset the power-on reset (porb) pin resets the device if forced low . the reset is asynchronous, the minimum low pulse width is 5 ns. reset is needed to initialize all of the register values to their defaul ts. reset must be asserted at power on, and may be re-asse rted at any time to restore defaults. this is implemented simply using an external capacitor to gnd along with the internal pull-up resistor. the ACS8522BT is held in a reset state for 250 ms after the porb pin has been pulled high . in normal operation porb should be held high . serial interface the ACS8522BT device has a serial interface which can be spi compatible. the motorola spi convention is that address and data are transmitted and received msb first. on the ACS8522BT, address and data are transmitted and received lsb first. address, read/write control and data on the sdi pin are latched into the device on the rising edge of the sclk. during a read operation, serial data output on the sdo pin can be read out of the device on either the rising or falling edge of the sclk depending on the logic level of clke. for standard motorola spi compliance, data should be clocked out of the sdo pin on the rising edge of the sclk so that it may be latched into the microprocessor on the falling edge of the sclk. figure 12 and figure 13 show the timing diagrams of write and read accesses for this interface. during read access, the output data sdo is clocked out on the rising edge of sclk when the active edge selection control bit clke is 0 and on the falling edge when clke is 1. the serial interface clock (sclk) is not required to run between accesses (i.e ., when csb = 1). figure 12 and figure 13 show the timing diagrams of read and write accesses for this mode.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 43 www.semtech.com figure 12 read access timing for serial interface table 19 read access timing for serial interface (see figure 12 ) symbol parameter min typ max t su1 setup sdi valid to sclk rising edge 4 ns - - t su2 setup csb falling edge to sclk rising edge 14 ns - - t d1 delay sclk rising edge (sclk falling edge for clke = 1) to sdo valid - - 18 ns t d2 delay csb rising edge to sdo high-z - - 16 ns t pw1 sclk low time 22 ns - - t pw2 sclk high time 22 ns - - t h1 hold sdi valid after sclk rising edge 6 ns - - t h2 hold csb low after sclk rising edge , for clke = 0 hold csb low after sclk falling edge , for clke = 1 5 ns - - t p time between consecutive accesses (csb rising edge to csb falling edge )10 ns - - f8526d_013readaccserial_01 sclk csb clke = 0; sdo data is clocked out on the rising edge of sclk clke = 1; sdo data is clocked out on the falling edge of sclk r/w output not driven, pulled low by internal resistor sdi sdo t su2 t su1 t h1 t pw1 t pw2 _ a0 a1 a2 a3 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 d7 t h2 t d2 t d1 sclk csb r/w output not driven, pulled low by internal resistor sdi sdo _ a0 a1 a2 a3 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 d7 t h2 t d2 t d1
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 44 www.semtech.com figure 13 write access timing for serial interface table 20 write access timing for serial interface (see figure 13 ) symbol parameter min typ max t su1 setup sdi valid to sclk rising edge 4 ns - - t su2 setup csb falling edge to sclk rising edge 14 ns - - t pw1 sclk low time 22 ns - - t pw2 sclk high time 22 ns - - t h1 hold sdi valid after sclk rising edge 6 ns - - t h2 hold csb low after sclk rising edge 5 ns - - t p time between consecutive accesses (csb rising edge to csb falling edge )10 ns - - sclk csb r/w output not driven, pulled low by internal resistor sdi sdo t su2 t su1 t h1 t pw1 t pw2 _ a0 a1 a2 a3 a4 a5 a6 t h2 d0 d1 d2 d3 d4 d5 d6 d7 f8525d_014writeaccserial_01
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 45 www.semtech.com each register, or register group, is described in the register map ( table 21 ) and the subsequent description tables. register organization the registers of the acs8522b are identified by name and corresponding hexadecimal address. they are presented here in ascending order of ad dress, and each register is organized with the most-significant bit in the left-most position, and bit significance decreasing towards the right-most bit. some registers carry separate data fields of various sizes, from single-bit values (e.g. flags) upwards. several data fields occupy mult iple registers, as shown in table 21 . shaded areas in the map are ?don?t care,? and writing to them will not affect any function of the device. bits labelled ?set to 0? or ?set to 1? must be set as stated during initialization of the de vice following power- up or power-on reset. failure to correctly set these bits may cause the device to operate in an unexpected way. caution! do not write to any undefine d register addresses as this may cause the device to operate in a test mode. if an undefined register has been inadvertently addressed, the device should be reset to ensure the undefined regist ers are at default values. multi-word registers for multi-word registers (e.g . reg. 70 and 71), all the words must be written to their separate addresses, without any other access taking place, before their combined value can take e ffect. if the sequence is interrupted, the sequence of writes will be ignored. reading a multi-word addre ss freezes the other address words of a multi-word address so that the bytes all correspond to the same complete word. register access most registers are of one of two types, configuration registers or status register s, the exceptions being the chip_id and chip_revision registers. configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). all status registers may be read at any time and, in some status registers (such as the sts_interrupts register). any individual data field can be cleared by writing a 1 into each bit of the field (writing a 0 does not affect the value of the bit). configuration registers each configuration register reverts to a default value on power-up or following a rese t. most default values are fixed, but some can be pin-se t. all configuration registers can be read out over the serial port. status registers the status registers contain readable registers. they may all be read from outside the chip but are not writeable from outside the chip (except for a clearing operation). all status registers are read vi a shadow registers to avoid data hits due to dynamic operation. interrupt enable and clear interrupt requests are flagged on pin intreq; the active state ( high or low ) is programmable and the pin can either be driven, or set to high impedance when non- active (reg 7d refers). bits in the interrupt status register are set ( high ) by the following conditions; 1. any reference source becoming valid or going invalid. 2. a change in the operating state (e.g. locked, holdover 3. a brief loss of the currentl y selected reference source. all interrupt sources, see reg. 05, reg. 06 and reg. 08, are maskable via the mask register, each one being enabled by writing a 1 to the appropriate bit. any unmasked bit set in the interr upt status register will cause the interrupt request pin to be asserted.all interrupts are cleared by writing a 1 to the bit(s) to be cleared in the status register. when all pe nding unmasked interrupts are cleared the interrupt pin will go inactive. defaults each register is given a defi ned default value at reset and these are listed in the map and description tables. however, some read-only status registers may not necessarily show the same de fault values after reset as those given in the tables. this is because they reflect the status of the device which ma y have changed in the time it takes to carry out the read, or through reasons of configuration. in the same way, the default values given for shaded areas could also take different values to those stated. register map
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 46 www.semtech.com table 21 register map register name address (hex) default (hex) data bit ro = read only r/w = read/write 7 (msb)6543210 (lsb) chip_id (ro) 00 4a device part number [7:0] 8 least significant bits of the chip id 01 21 device part number [15:8] 8 most significant bits of the chip id chip_revision (ro) 02 00 chip revision number [7:0] test_register1 (r/w, bit 7 ro) 03 14 phase_alarm disable_180 resync_ analog set to zero 8k edge polarity set to zero set to zero sts_interrupts (r/w) 05 ff sec3 valid change sec2 valid change sec1 valid change 06 3f operating_ mode main_ref_ failed sec4 valid change sts_current_dpll_frequency, see oc/od 07 00 bits [18:16] of current dpll frequency sts_interrupts (r/w) 08 50 t4_status sts_operating (ro) 09 41 t4_dpll_lock t0_dpll_freq _soft_alarm t4_dpll_freq _soft_alarm t0_dpll_operating_mode sts_priority_table (ro) 0a 00 highest priority validated source currently selected source 0b 00 3 rd highest priority validated source 2 nd highest priority validated source sts_current_dpll_frequency [7:0] 0c 00 bits [7:0] of current dpll frequency (ro) [15:8] 0d 00 bits [15:8] of current dpll frequency [18:16] 07 00 bits [18:16] of current dpll frequency sts_sources_valid (ro) 0e 00 sec3 sec2 sec1 0f 00 sec4 sts_reference_sources (ro) status of inputs: out-of-band alarm (soft) out-of-band alarm (hard) no activity alarm phase lock alarm out-of-band alarm (soft) out-of band alarm (hard) no activity alarm phase lock alarm inputs sec1 & sec2 11 66 status of sec2 input status of sec1 input sec3 13 66 status of sec3 input sec4 14 66 status of sec4 input cnfg_ref_selection_priority (r/w) (sec2 & sec1) 19 32 programmed_priority programmed_priority (sec3) 1b 40 programmed_priority (sec4) 1c 05 programmed_priority cnfg_enet_freq (r/w) 20 00 enet_2k_ enable enet_pll_ enable 01_enet 04_enet 03_enet 02_enet cnfg_ref_source_frequency (r/w) (sec1) 22 00 divn_sec1 lock8k_sec1 bucket_id_sec1 reference_source_frequency_sec1 (sec2) 23 00 divn_sec2 lock8k_sec2 bucket_id_sec2 reference_source_frequency_sec2 (sec3) 27 03 divn_sec3 lock8k_sec3 bucket_id_sec3 reference_source_frequency_sec3 (sec4) 28 03 divn_sec4 lock8k_sec4 bucket_id_sec4 reference_source_frequency_sec4 cnfg_operating_mode (r/w) 32 00 to_dpll_operating_mode force_select_reference_source (r/w) 33 0f forced_reference_source cnfg_input_mode (r/w) 34 ca set to zero phalarm_ timeout xo_ edge man_holdover extsync_en ip_sonsdhb reversion_ mode cnfg_t4_path (r/w) 35 40 lock_t4_to t0 t4_dig_ feedback t4_forced_reference_source cnfg_dig_outputs_sonsdh (r/w) 38 0d dig2_sonsdh dig1_sonsdh cnfg_digtial_frequencies (r/w) 39 08 d igital2_frequency digital1_frequency cnfg_differential_outputs (r/w) 3a c2 o1_lvds_pecl cnfg_auto_bw_sel 3b fd auto_bw_sel t0_lim_int cnfg_nominal_frequency [7:0] 3c 99 nominal frequency [7:0] (r/w) [15:8] 3d 99 nominal frequency [15:8] cnfg_holdover_frequency [7:0] 3e 00 holdover frequency [7:0] (r/w) [15:8] 3f 00 holdover frequency [15:8] cnfg_holdover_modes (r/w) 40 88 auto_ averaging fast_averaging read_average mini_holdo ver_mode holdover frequency [18:16] (with registers 3e and 3f above) cnfg_dpll_freq_limit (r/w) [7:0] 41 76 dpll frequency offset limit [7:0] [9:8] 42 00 dpll frequency offset limit [9:8] cnfg_interrupt_mask (r/w) [7:0] 43 00 sec3 interrupt not masked sec2 interrupt not masked sec1 interrupt not masked
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 47 www.semtech.com [15:8] 44 00 operating_ mode interrupt not masked main_ref_ failed interrupt not masked sec4 interrupt not masked cnfg_interrupt_mask cont.[23:16] 45 00 t4_status interrupt not masked cnfg_freq_divn (r/w) [7:0] 46 ff divn_value [7:0] [13:8] 47 3f divn_value [13:8] cnfg_monitors (r/w) 48 05 f req_mon_clk los_flag_ on_ tdo ultra_fast_ switch ext_switch pbo_freeze pbo_en freq_monitor_ soft_enable freq_monitor_ hard_enable cnfg_freq_mon_threshold (r/w) 49 23 soft_frequency_alarm_ threshold [3:0] hard_frequency_alarm_threshold [3:0] cnfg_current_freq_mon_ threshold (r/w) 4a 23 current_soft_frequency_alarm_threshold [3:0] current_hard_frequency_alarm_threshold [3:0] cnfg_registers_source_select (r/w) 4b 00 t4_t0_select frequency_measurement_channel_select [3:0] sts_freq_measurement (ro) 4c 00 freq_measurement_value [7:0] cnfg_dpll_soft_limit (r/w) 4d 8e freq limit phase loss enable dpll frequency soft alarm limit [6:0] resolution = 0.628 ppm cnfg_upper_threshold_0 (r/w) 50 06 leaky bucket conf iguration 0: activity al arm set threshold [7:0] cnfg_lower_threshold_0 (r/w) 51 04 leaky bucket conf iguration 0: activity al arm reset threshold [7:0] cnfg_bucket_size_0 (r/w) 52 08 leaky bucket config uration 0: activity alarm bucket size [7:0] cnfg_decay_rate_0 (r/w) 53 01 leaky bucket cfg 0: decay_rate [1:0] cnfg_upper_threshold_1 (r/w) 54 06 leaky bucket conf iguration 1: activity al arm set threshold [7:0] cnfg_lower_threshold_1 (r/w) 55 04 leaky bucket conf iguration 1: activity al arm reset threshold [7:0] cnfg_bucket_size_1 (r/w) 56 08 leaky bucket config uration 1: activity alarm bucket size [7:0] cnfg_decay_rate_1 (r/w) 57 01 leaky bucket cfg 1: decay_rate [1:0] cnfg_upper_threshold_2 (r/w) 58 06 leaky bucket conf iguration 2: activity al arm set threshold [7:0] cnfg_lower_threshold_2 (r/w) 59 04 leaky bucket conf iguration 2: activity al arm reset threshold [7:0] cnfg_bucket_size_2 (r/w) 5a 08 leaky bucket config uration 2: activity alarm bucket size [7:0] cnfg_decay_rate_2 (r/w) 5b 01 leaky bucket cfg 2: decay_rate [1:0] cnfg_upper_threshold_3 (r/w) 5c 06 leaky bucket conf iguration 3: activity al arm set threshold [7:0] cnfg_lower_threshold_3 (r/w) 5d 04 leaky bucket conf iguration 3: activity al arm reset threshold [7:0] cnfg_bucket_size_3 (r/w) 5e 08 leaky bucket config uration 3: activity alarm bucket size [7:0] cnfg_decay_rate_3 (r/w) 5f 01 leaky bucket cfg 3: decay_rate [1:0] cnfg_output_frequency (01 & 02) (r/w) 60 80 output_freq_02 (o3) 61 06 output_freq_o3 (04) 62 84 output_freq_01 output_freq_o4 (mfrsync) 63 c0 mfrsync_en frsync_en cnfg_t4_dpll_frequency (r/w) 64 05 t4_dpll_frequency cnfg_t0_dpll_frequency (r/w) 65 01 t4 for measuring t0 phase t4 apll for t0 e1/ds1 t0 freq to t4 apll t0_dpll_frequency cnfg_t4_dpll_bw (r/w) 66 00 t4_dpll_bandwidth [1:0] cnfg_t0_dpll_locked_bw (r/w) 67 0d t0_dpll_locked_bandwidth [4:0] cnfg_t0_dpll_acq_bw (r/w) 69 0f t0_acquisition_bandwidth [4:0] cnfg_t4_dpll_damping (r/w) 6a 13 t4_pd2_gain_alog_8k [6:4] t4_damping [2:0] cnfg_t0_dpll_damping (r/w) 6b 13 t0_pd2_gain_alog_8k [6:4] t0_damping [2:0] cnfg_t4_dpll_pd2_gain (r/w) 6c c2 t4_pd2_gain_ enable t4_pd2_gain_alog [6:4] t4_pd2_gain_digital [2:0] cnfg_t0_dpll_pd2_gain (r/w) 6d c2 t0_pd2_gain_ enable t0_pd2_gain_alog [6:4] t0_pd2_gain_digital [2:0] cnfg_phase_offset (r/w) [7:0] 70 00 phase_offset_value[7:0] [15:8] 71 00 phase_offset_value[15:8] cnfg_pbo_phase_offset (r/w) 72 00 pbo_phase_offset [5:0] table 21 register map (cont...) register name address (hex) default (hex) data bit ro = read only r/w = read/write 7 (msb)6543210 (lsb)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 48 www.semtech.com cnfg_phase_loss_fine_limit (r/w) 73 a2 fine limit phase loss enable (1) no activity for phase loss test bit set to 1 phase_loss_fine_limit [2:0] cnfg_phase_loss_coarse_limit (r/w) 74 85 coarse limit phase loss enable (2) wide range enable enable multi phase resp. phase loss coarse limit in ui pk-pk [3:0] cnfg_phasemon (r/w) 76 06 input noise window enable sts_current_phase (ro) [7:0] 77 00 current_phase[7:0] [15:8] 78 00 current_phase[15:8] cnfg_phase_alarm_timeout (ro) 79 32 timeout value in 2s intervals [5:0] cnfg_sync_pulses (r/w) 7a 00 2k_8k_from_ t4 8k_invert 8k_pulse 2k_invert 2k_pulse cnfg_sync_phase (r/w) 7b 00 indep_frsync/ mfrsync sync_oc-n_ rates sync_phase cnfg_sync_monitor (r/w) 7c 2b ph_offset_ ramp cnfg_interrupt (r/w) 7d 02 gpo interrupt enable interrupt tristate enable interrupt polarity enable cnfg_protection(r/w) 7e 85 protection_value table 21 register map (cont...) register name address (hex) default (hex) data bit ro = read only r/w = read/write 7 (msb)6543210 (lsb)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 49 www.semtech.com register descriptions address (hex): 00 register name chip_id description (ro) 8 least significant bits of the chip id. default value 0100 1010 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 chip_id[7:0] bit no. description bit value value description [7:0] chip_id least significant byte of the 2-byte device id 4a (hex) address (hex): 01 register name chip_id description (ro) 8 most significant bits of the chip id. default value 0010 0001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 chip_id[15:8] bit no. description bit value value description [7:0] chip_id most significant byte of the 2-byte device id 21 (hex) address (hex): 02 register name chip_revision description (ro) silicon revision of the device. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 chip_revision[7:0] bit no. description bit value value description [7:0] chip_revision silicon revision of the device 00 (hex)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 50 www.semtech.com address (hex): 03 register name test_register1 description (r/w) register containing various test controls (not normally used). default value 0001 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 phase_alarm disable_180 resync_analog set to zero 8k edge polarity set to zero set to zero bit no. description bit value value description 7 phase_alarm ( phase alarm (r/o)) instantaneous result from t0 dpll 0 1 t0 dpll reporting phase locked. t0 dpll reporting phase lost. 6 disable_180 normally the dpll will try to lock to the nearest edge (180 ? ) for the first 2 seconds when locking to a new reference. if the dpll does not determine that it is phase locked after this time, then the capture range reverts to 360 ? , which corresponds to frequency and phase locking. forcing the dpll into frequency locking mode may reduce the time to frequency lock to a new reference by up to 2 seconds. however, this may cause an unnecessary phase shift of up to 360 ? when the new and old references are very close in frequency and phase. 0 1 t0 dpll automatically determines frequency lock enable. t0 dpll forced to always frequency and phase lock. 5not used. - - 4 resync_analog (analog dividers re-synchronization) the analog output dividers include a synchronization mechanism to ensure phase lock at low frequencies between the input and the output. 0 1 analog divider only sync hronized during first 2 seconds after power-up. analog dividers always sy nchronized.this keeps the clocks divided down from the apll output, in sync with equivalent frequency di gital clocks in the dpll. hence ensuring that 6.48 mhz output clocks, and above, are in sync with the dpll even though only a 77.76 mhz clock drives the apll. 3 test control leave unchanged or set to 0 0- 2 8k edge polarity when lock 8k mode is selected for the current input reference source, this bit allows the system to lock on either the rising or th e falling edge of the input clock. 0 1 lock to falling clock edge. lock to rising clock edge. 1 test control leave unchanged or set to zero 0- 0 test control leave unchanged or set to zero 0-
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 51 www.semtech.com address (hex): 05 register name sts_interrupts description (r/w) bits [7:0] of the interrupt status register. default value 1111 1111 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sec3 valid change sec2 valid change sec1 valid change bit no. description bit value value description 7 sec3 valid change interrupt indicating that input sec3 has become valid (if it was invalid), or invalid (if it was valid). latched until reset by software writing a 1 to this bit. 0 1 input sec3 has not changed status (valid/invalid). input sec3 has changed status (valid/invalid). writing 1 resets the input to 0. [6:4] not used. - - 3 sec2 valid change interrupt indicating that input sec2 has become valid (if it was invalid), or invalid (if it was valid). latched until reset by software writing a 1 to this bit. 0 1 input sec2 has not changed status (valid/invalid). input sec2 has changed status (valid/invalid). writing 1 resets the input to 0. 2 sec1 valid change interrupt indicating that input sec1 has become valid (if it was invalid), or invalid (if it was valid). latched until reset by software writing a 1 to this bit. 0 1 input sec1 has not changed status (valid/invalid). input sec1 has changed status (valid/invalid). writing 1 resets the input to 0. [1:0] not used. - - address (hex): 06 register name sts_interrupts description (r/w) bits [15:8] of the interrupt status register. default value 0111 1111 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 operating_ mode main_ref_failed sec4 valid change bit no. description bit value value description 7 operating_mode interrupt indicating that the operating mode has changed. latched until reset by software writing a 1 to this bit. 0 1 operating mode has not changed. operating mode has changed. writing 1 resets the input to 0. 6 main_ref_failed interrupt indicating that input to the t0 dpll has failed. this interrupt will be raised after 2 missing input cycles. this is much quicker than waiting for the input to become invalid. this input is not generated in free-run or holdover modes. latched until reset by software writing a 1 to this bit. 0 1 input to the t0 dpll is valid. input to the t0 dpll has failed. writing 1 resets the input to 0. [5:1] not used. - -
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 52 www.semtech.com 0 sec4 valid change interrupt indicating that input sec4 has become valid (if it was invalid), or invalid (if it was valid). latched until reset by software writing a 1 to this bit. 0 1 input sec4 has not changed status (valid/invalid). input sec4 has changed status (valid/invalid). writing 1 resets the input to 0. address (hex): 07 register name sts_current_dpll_frequency [18:16] description (ro) bits [18:16] of the current dpll frequency. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sts_current_dpll_frequency[18:16] bit no. description bit value value description [7:3] not used. - - [2:0] sts_current_dpll_frequency[18:16] when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the frequency for the t0 path is reported. when this bit 4 = 1 the frequency for the t4 path is reported. - see register description of sts_current_dpll_frequency at address 0d hex. address (hex): 08 register name sts_interrupts description (r/w) bits [23:16] of the interrupt status register. default value 0101 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_status bit no. description bit value value description 7not used. - - 6 t4_status interrupt indicating that the t4 dpll has lost lock (if it was locked) or gained lock (if it was not locked). latched until reset by software writing a 1 to this bit. 0 1 input to the t4 dpll has not changed. input to the t4 dpll has lost/gained lock. writing 1 resets the input to 0. [5:0] not used. - - address (hex): 06 (cont...) register name sts_interrupts description (r/w) bits [15:8] of the interrupt status register. default value 0111 1111 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 operating_ mode main_ref_failed sec4 valid change bit no. description bit value value description
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 53 www.semtech.com address (hex): 09 register name sts_operating description (ro) current operating state of the device?s internal state machine. default value 0100 0001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_dpll_lock t0_dpll_freq_ soft_alarm t4_dpll_freq_ soft_alarm t0_dpll_operating_mode bit no. description bit value value description 7not used. - - 6 t4_dpll_lock reports current phase lock status of the t4 dpll. the t4 dpll does not have the same state machine as the t0 dpll, as it does not support all the features of the to dpll. it can only report its state as locked or unlocked. the bit indicates that the t4 dpll is locked by monitoring the t4 dpll phase loss indicators, which potentially come from four sources. the four phase loss indicators are enabled by the same registers that enable them for the t0 dpll, as follows: the fine phase loss detector enabled by reg. 73 bit 7, the coarse phase loss detector enabled by reg. 74 bit 7, the phase loss indication from no activity on the input enabled by reg. 73 bit 6 and phase loss from the dpll being at its minimum or maximum frequency limits enabled by reg. 4d bit 7. for the t4 dpll lock indicator (at reg. 09 bit 6) the bit will latch an indication of phase lost from the coarse phase lock detector such that when an indication of phase lost (or not locked) is set it stays in that phase lost or not locked state (so reg. 09 bit 6 =0). for this bit to give a corr ect current reading of the t4 dpll locked state, then the coarse phase loss detector should be temporarily disabled (set reg. 74 bit 7 = 0), then the t4 locked bit can be read (reg. 09 bit 6), then the coarse phase loss detector should be re-enabled again (set reg. 74 bit 7 = 1). once the bit is indicating ?locked? (reg. 09 bit 6=1), it is always a correct indication and no change to the coarse phase loss detect or enable is required. if at any time any cycle slips occur that trigger the coarse phase loss detector (which monitors cycle slips) then this information is latched so that the lock bit (reg. 09 bit 6) will go low and stay low, indicating that a problem has occurred. it is then a requirement that the coarse phase loss detector's disable/re-enable sequence is performed during a read of the t4 locked bit, in order to get a current indication of whether the t4 dpll is locked. 0 1 t4 dpll not phase locked to reference source. t4 dpll phase locked to reference source.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 54 www.semtech.com 5 t0_dpll_freq_soft_alarm the t0 dpll has a programmable frequency limit and ?soft? alarm limit. the frequency limit is the extent to which it will track a reference before limiting. the ?soft? limit is the point beyond which the dpll tracking a reference will cause an alarm. this bit reports the status of the ?soft? alarm. 0 1 t0 dpll tracking its refere nce within the limits of the programmed ?soft? alarm. t0 dpll tracking its reference beyond the limits of the programmed ?soft? alarm. 4 t4_dpll_freq_soft_alarm the t4 dpll has a programmable frequency limit and ?soft? alarm limit. the frequency limit is the extent to which it will track a reference before limiting. the ?soft? limit is the point beyond which the dpll tracking a reference will cause an alarm. this bit reports the status of the ?soft? alarm. 0 1 t4 dpll tracking its refere nce within the limits of the programmed ?soft? alarm. t4 dpll tracking its reference beyond the limits of the programmed ?soft? alarm. 3not used. - - [2:0] t0_dpll_operating_mode this field is used to report the state of the internal finite state machine controlling the t0 dpll. 000 001 010 011 100 101 110 111 not used. free run. holdover. not used. locked. pre-locked2. pre-locked. phase lost. address (hex): 09 (cont...) register name sts_operating description (ro) current operating state of the device?s internal state machine. default value 0100 0001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_dpll_lock t0_dpll_freq_ soft_alarm t4_dpll_freq_ soft_alarm t0_dpll_operating_mode bit no. description bit value value description
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 55 www.semtech.com address (hex): 0a register name sts_priority_table description (ro) bits [7:0] of the validated priority table. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 highest priority validated so urce currently selected source bit no. description bit value value description [7:4] highest priority validated source reports the input channel number of the highest priority validated source. when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the highest priority validated source for the t0 path is reported. when this bit 4 = 1 the highest priority validated source for the t4 path is reported. 0000 0011 0100 1000 1001 no valid source available. input sec1 is the highes t priority valid source. input sec2 is the highes t priority valid source. input sec3 is the highes t priority valid source. input sec4 is the highes t priority valid source. [3:0] currently selected source reports the input channel number of the currently selected source. when in non-revertive mode, this is not necessarily the same as the highest priority validated source. when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the currently selected source for the t0 path is reported. when this bit 4 = 1 the currently selected source for the t4 path is reported. the t4 path does not have a non-revertive mode so this will always be the same as the highest priority validated source. 0000 0011 0100 1000 1001 all other values no source currently selected. input sec1 is the currently selected source. input sec2 is the currently selected source. input sec3 is the currently selected source. input sec4 is the currently selected source. not used.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 56 www.semtech.com address (hex): 0b register name sts_priority_table description (ro) bits [15:8] of the validated priority table. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 3 rd highest priority validated source 2 nd highest priority validated source bit no. description bit value value description [7:4] 3 rd highest priority validated source reports the input channel number of the 3 rd highest priority validated source. when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the 3 rd highest priority validated source for the t0 path is reported. when this bit 4 = 1 the value will always be zero as the t4 path does not maintain the 3 rd highest priority validated source. 0000 0011 0100 1000 1001 all other values no source currently selected. input sec1 is the currently selected source. input sec2 is the currently selected source. input sec3 is the currently selected source. input sec4 is the currently selected source. not used. [3:0] 2 nd highest priority validated reports the input channel number of the 2 nd highest priority validated source. when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the 2 nd highest priority validated source for the t0 path is reported. when this bit 4 = 1 the 2 nd highest priority validated source for the t4 path is reported. 0000 0011 0100 1000 1001 all other values no source currently selected. input sec1 is the currently selected source. input sec2 is the currently selected source. input sec3 is the currently selected source. input sec4 is the currently selected source. not used. address (hex): 0c register name sts_current_dpll_frequency [7:0] description (ro) bits [7:0] of the current dpll frequency. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bits [7:0] of sts_current_dpll_frequency bit no. description bit value value description [7:0] bits [7:0] of sts_current_dpll_frequency when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the frequency for the t0 path is reported. when this bit 4 = 1 the frequency for the t4 path is reported. - see register description of sts_current_dpll_frequency at address 0d hex.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 57 www.semtech.com address (hex): 0d register name sts_current_dpll_frequency [15:8] description (ro) bits [15:8] of the current dpll frequency. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sts_current_dpll_frequency[15:8] bit no. description bit value value description [7:0] sts_current_dpll_frequency[15:8] this value in this register is combined with the value in reg. 0c and reg. 07 to represent the current frequency offset of the dpll. when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the frequency for the t0 path is reported. when this bit 4 = 1 the frequency for the t4 path is reported. - in order to calculate the ppm offset of the dpll with respect to the crystal oscill ator frequency, the value in reg. 07, reg. 0d and reg. 0c must be concatenated. this value is a 2?s complement signed integer. the value multiplied by 0.0003068 dec. will give the value in ppm offset with respect to the xo frequency, allowing for any crystal calibration that has been performed, via cnfg_nominal_frequency , reg. 3c and 3d. the value is actually the dpll integral path value so it can be viewed as an average frequency, where the rate of change is related to the dpll bandwidth. if bit 3 of reg. 3b is high then this value will freeze if the dpll has been pulled to its min. or max. frequency. address (hex): 0e register name sts_sources_valid description (ro) 8 least significant bits of the sts_sources_valid register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sec3 sec2 sec1 bit no. description bit value value description 7 sec3 bit indicating if sec3 is valid. the input is valid if either it has no outstanding alarms, or it only has a soft frequency alarm. 0 1 input sec3 is invalid. input sec3 is valid. [6:4] not used. - - 3 sec2 bit indicating if sec2 is valid. the input is valid if either it has no outstanding alarms, or it only has a soft frequency alarm. 0 1 input sec2 is invalid. input sec2 is valid. 2 sec1 bit indicating if sec1 is valid. the input is valid if either it has no outstanding alarms, or it only has a soft frequency alarm. 0 1 input sec1 is invalid. input sec1 is valid. [1:0] not used. - -
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 58 www.semtech.com address (hex): 0f register name sts_sources_valid description (ro) 8 most significant bits of the sts_sources_valid register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sec4 bit no. description bit value value description [7:1] not used. - - 0 sec4 bit indicating if sec4 is valid. the input is valid if either it has no outstanding alarms, or it only has a soft frequency alarm. 0 1 input sec4 is invalid. input sec4 is valid. address (hex): 11 register name sts_reference_sources inputs sec1 & sec2 description (ro except for test when r/w) reports any alarms active on inputs. default value 0110 0110 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 address 11: status of sec2 input address 13: status of sec3 input address 11: status of sec1 input address 14: status of sec4 input out-of-band alarm (soft) out-of-band alarm (hard) no activity alarm phase lock alarm out-of-band alarm (soft) out-of band alarm (hard) no activity alarm phase lock alarm bit no. description bit value value description 7 & 3 out-of-band alarm (soft) soft out-of-band alarm bit for input. a ?soft? alarm will not invalidate an input. 0 1 no alarm. alarm armed. alarm thresholds set by reg. 49 bits [7:4], or by reg. 4a bits 7:4 if the input is currently selected. 6 & 2 out-of-band alarm (hard) hard out-of-band alarm bit for input. a ?hard? alarm will invalidate an input. 0 1 no alarm. alarm armed. alarm thresholds set by reg. 49 bits [3:0], or by reg. 4a bits [3:0] if the input is currently selected. 5 & 1 no activity alarm alarm indication from the activity monitors. 0 1 no alarm. input has an active no activity alarm. 4 & 0 phase lock alarm if the dpll can not indicate that it is phase locked onto the current source within 100 seconds this alarm will be raised. 0 1 no alarm. phase lock alarm. address (hex): 13 as reg. 11, but for sts_reference_sources, input sec3 default value: 0110 0110 address (hex): 14 as reg. 11, but for sts_reference_sources, input sec4 default value: 0110 0110
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 59 www.semtech.com address (hex): 19 register name cnfg_ref_selection_priority (sec2 & sec1) description (r/w) configures the relative priority of input sources sec2 and sec1. default value *(to) *(t4) 0011 0010 0011 0010 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 cnfg_ref_selection_priority_sec2 cnfg_ref_selection_priority_sec1 bit no. description bit value value description [7:4] cnfg_ref_selection_priority_sec2 this 4-bit value represents the relative priority of input sec2. the smaller the number, the higher the priority; zero disables the input. *when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the priority for the t0 path is configured. when this bit 4 = 1 the priority for the t4 path is configured. 0000 0001-1111 input sec2 unavailable for automatic selection. input sec2 priority value. [3:0] cnfg_ref_selection_priority_sec1 this 4-bit value represents the relative priority of input sec1. the smaller the number, the higher the priority; zero disables the input. *when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the priority for the t0 path is configured. when this bit 4 = 1 the priority for the t4 path is configured. 0000 0001-1111 input sec1 unavailable for automatic selection. input sec1 priority value. address (hex): 1b register name cnfg_ref_selection_priority (sec3) description (r/w) configures the relative priority of input source sec3. default value *(t0) *(t4) 0100 0000 0101 0100 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 cnfg_ref_selection_priority_sec3 bit no. description bit value value description [7:4] cnfg_ref_selection_priority_sec3 this 4-bit value represents the relative priority of input sec3. the smaller the number, the higher the priority; zero disables the input. *when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the priority for the t0 path is configured. when this bit 4 = 1 the priority for the t4 path is configured. 0000 0001-1111 input sec3 unavailable for automatic selection. input sec3 priority value. [3:0] not used. - -
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 60 www.semtech.com address (hex): 1c register name cnfg_ref_selection_priority (sec4) description (r/w) configures the relative priority of input source sec4. default value *(t0) *(t4) 0000 0101 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 cnfg_ref_selection_priority_sec4 bit no. description bit value value description [7:4] not used. - - [3:0] cnfg_ref_selection_priority_sec4 this 4 bit value represents the relative priority of input sec4. the smaller the number, the higher the priority; zero disables the input. *when bit 4 ( t4_t0_select ) of reg. 4b ( cnfg_registers_source_select ) = 0 the priority for the t0 path is configured. when this bit 4 = 1 the priority for the t4 path is configured. 0000 0001-1111 input sec4 unavailable for automatic selection. input sec4 priority value.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 61 www.semtech.com address (hex): 20 register name cnfg_enet_freq description (r/w) register to enable ethernet frequencies on to outputs 01 through 04. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 enet_2k_ enable enet_pll_ enable o1_enet o4_enet o3_enet o2_enet bit no. description bit value value description 7 enet_2k_enable 0 disable sync2k alignment of ethernet clocks 1 enable sync2k alignment of ethernet clocks 6 enet_pll_enable 0 ethernet frequencies apll enabled 1 ethernet frequenc ies apll disabled 5 01_enet 0 01 output is non-ethernet frequency as described in reg. 62. 1 01 output is ethernet derived as described in reg. 62. 4 04_enet 0 04 output is non-ethernet frequency as described in reg. 62. 1 04 output is ethernet derived as described in reg. 62. 3 not used -- 2 o3_enet 0 03 output is non-ethernet frequency as described in reg. 61. 1 03 output is ethernet derived as described in reg. 61. 1 o2_enet 0 02 output is non-ethernet frequency as described in reg. 60. 1 02 output is ethernet derived as described in reg. 60. 0 not used --
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 62 www.semtech.com address (hex): 22 use = 1 register name cnfg_ref_source_frequency sec, where for reg 22, = 1 description (r/w) configuration of the frequency and input monitoring for input sec. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 divn_sec lock8k_sec bucket_id_sec reference_source_frequency_sec bit no. description bit value value description 7 divn_sec this bit selects whether or not input sec is divided in the programmable pre-divider prior to being input to the dpll and frequency monitor- see reg. 46 and reg. 47 ( cnfg_freq_divn ). 0 1 input sec fed directly to dpll and monitor. input sec fed to dp ll and monitor via pre- divider. 6 lock8k_sec this bit selects whether or not input sec is divided in the preset pre-divider prior to being input to the dpll. this results in the dpll locking to the reference after it has been divided to 8 khz. this bit is ignored when divn_sec is set (bit =1). 0 1 input sec fed directly to dpll. input sec fed to dpll via preset pre-divider. [5:4] bucket_id_sec every input has its own leaky bucket used for activity monitoring. th ere are four possible configurations for each leaky bucket- see reg. 50 to reg. 5f. this 2-bit field selects the configuration used for input sec. 00 01 10 11 input sec activity monitor uses leaky bucket configuration 0. input sec activity monitor uses leaky bucket configuration 1. input sec activity monitor uses leaky bucket configuration 2. input sec activity monitor uses leaky bucket configuration 3. [3:0] reference_source_frequency_sec programs the frequency of the reference source connected to input sec. if divn_sec is set, then this value should be set to 0000 (8 khz). 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011-1111 8 khz. 1544/2048 khz (dependant on bit 2 ( ip_sonsdhb ) in reg. 34). 6.48 mhz. 19.44 mhz. 25.92 mhz. 38.88 mhz. 51.84 mhz. 77.76 mhz. not used. 2 khz. 4 khz. not used. address (hex): 23 use description for reg. 22, but use = 2 default value: 0000 0000 address (hex): 27 use description for reg. 22, but use = 3 default value: 0000 0011 address (hex): 28 use description for reg. 22, but use = 4 default value: 0000 0011
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 63 www.semtech.com address (hex): 32 register name cnfg_operating_mode description (r/w) register to force the state of the to dpll controlling state machine. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t0_dpll_operating_mode bit no. description bit value value description [7:3] not used. - - [2:0] t0_dpll_operating_mode this field is used to contro l the state of the internal finite state machine controlling the t0 dpll. a value of zero is used to allow the finite state machine to control itself. any other value will force the state machine to jump into that state. care should be taken when forcing the state machine. whilst it is forced, the internal monitoring functions cannot affect the internal state machine, therefore, the user is responsible for all monitoring and control functions required to achieve the desired functionality. 000 001 010 011 100 101 110 111 automatic (internal state machine controlled). free run. holdover. not used. locked. pre-locked2. pre-locked. phase lost. address (hex): 33 register name force_select_reference_source description (r/w) register used to force the selection of a particular reference source for the t0 dpll. default value 0000 1111 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 forced_reference_source bit no. description bit value value description [7:4] not used. - - [3:0] forced_reference_source value representing the source to be selected by the t0 dpll. value of 0 hex will leave the selection to the automatic control mechanism within the device. using this mechanism will bypass all the monitoring functions assuming the selected input to be valid. if the device is not in state ?locked? then it will progress to state locked in the usual manner. if the input fails, the device will not change state to holdover, as it is not allowed to disqualify the source. the effect of this register is simply to raise the priority of the selected input reference to ?1? (highest). to ensure selection of the programmed input reference under all circumstances, revertive mode should be enabled (reg. 34 bit 0 set to ?1?). 0000 0011 0100 1000 1001 1111 all other values automatic state machine source selection t0 dpll forced to select input sec1. t0 dpll forced to select input sec2. t0 dpll forced to select input sec3. t0 dpll forced to select input sec4. automatic. not used.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 64 www.semtech.com address (hex): 34 register name cnfg_input_mode description (r/w) register co ntrolling various input modes of the device. default value 1100 1010 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 set to 0 phalarm_time- out xo_edge man_holdover ex tsync_en ip_sonsdhb reversion_mode bit no. description bit value value description 7 set to 0. 0 set to 0. 6 phalarm_timeout bit to enable the automatic timeout facility on phase alarms. when enabled, any source with a phase alarm set will have its phase alarm cancelled after 128 seconds. 0 1 phase alarms on sources only cancelled by software. phase alarms on sources automatically time out. 5 xo_edge if the 12.800 mhz oscillator module connected to refclk has one edge faster than the other, then for jitter performance reasons, the faster edge should be selected. this bit allows either the rising edge or the falling edge to be selected. 0 1 device uses the rising edge of the external oscillator. device uses the falling edge of the external oscillator. 4 man_holdover bit to select whether or not the holdover frequency is taken directly from reg. 3e/reg. 3f/reg. 40 ( cnfg_holdover_frequency ). if this bit is set then it overrides any other holdover control bits. 0 1 holdover frequency is determined automatically. holdover frequency is taken from cnfg_holdover_frequency register. 3 extsync_en bit to select whether or not the t0 dpll will look for a reference sync pulse on the sync2k input pin. even though this bit may enable the external sync reference, it may be disabled according to auto_extsync_en . 0 1 no external sync signal- sync2k pin ignored. external sync derived from sync2k pin according to auto_extsync_en . 2 ip_sonsdhb bit to configure input frequencies to be either sonet or sdh derived. this applies only to selections of 0001 (bin) in the cnfg_ref_source_frequency registers when the input frequency is either 1544 khz or 2048 khz. 0 1 sdh- inputs set to 0001 expected to be 2048 khz. sonet- inputs set to 0001 expected to be 1544 khz. 1not used. - - 0 reversion_mode bit to select revertive/non-revertive mode. when in non-revertive mode, the device will not automatically switch to a higher priority source, unless the current source fails. when in revertive mode the device will always select the highest priority source. 0 1 non-revertive mode. revertive mode.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 65 www.semtech.com address (hex): 35 register name cnfg_t4_path description register to configure the inputs and other features in the t4 path. default value 0100 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 lock_t4_to_t0 t4_dig_feed- back t4_forced_reference_source bit no. description bit value value description 7 lock_t4_to_t0 bit selects either the t4 direct inputs, or t0 dpll as the input of the t4 path. this allows the t4 dpll to be used to produce different sets of frequencies to the t0 dpll but still maintain lock. 0 1 t4 path locks independently from the t0 path. t4 dpll locks to the output of the t0 dpll. 6 t4_dig_feedback bit to select digital feedback mode for the t4 dpll. 0 1 t4 dpll in analog feedback mode. t4 dpll in digital feedback mode. [5:4] not used. - - [3:0] t4_forced_reference_source this field can be used to force the t4 dpll to select a particular input. a value of zero in this field allows the t4 input to be selected automatically via the priority and input monitoring functions. 0000 0011 0100 1000 1001 all other values t4 dpll automatic source selection. t4 dpll forced to select input sec1. t4 dpll forced to select input sec2. t4 dpll forced to select input sec3. t4 dpll forced to select input sec4. not used. address (hex): 38 register name cnfg_dig_outputs_sonsdh description configures digital1 and digital2 output frequencies to be sonet or sdh compatible frequencies. default value 0000 1101* bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 dig2_sonsdh dig1_sonsdh bit no. description bit value value description 7not used. - - 6 dig2_sonsdh selects whether the frequencies generated by the digital2 frequency generator are sonet derived or sdh. *default value of this bit is set by the sonsdhb pin at power-up. 1 0 digital2 can be selected from 1544/3088/6176/ 12352 khz. digital2 can be selected from 2048/4096/8192/ 16384 khz. 5 dig1_sonsdh selects whether the frequencies generated by the digital1 frequency generator are sonet derived or sdh. *default value of this bit is set by the sonsdhb pin at power-up. 1 0 digital1 can be selected from 1544/3088/6176/ 12352 khz. digital1 can be selected from 2048/4096/8192/ 16384 khz. [4:0] not used. - -
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 66 www.semtech.com address (hex): 39 register name cnfg_digtial_frequencies description (r/w) configures the actual frequencies of digital1 & digital2. default value 0000 1000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 digital2_frequency digital1_frequency bit no. description bit value value description [7:6] digital2_frequency configures the frequency of digital2 . whether this is sonet or sdh based is configured by bit 6 ( dig2_sonsdh ) of reg. 38. 00 01 10 11 digital2 set to 1544 khz or 2048 khz. digital2 set to 3088 khz or 4096 khz. digital2 set to 6176 khz or 8192 khz. digital2 set to 12353 khz or 16384 khz. [5:4] digital1_frequency configures the frequency of digital1 . whether this is sonet or sdh based is configured by bit 5 ( dig1_sonsdh ) of reg. 38. 00 01 10 11 digital1 set to 1544 khz or 2048 khz. digital1 set to 3088 khz or 4096 khz. digital1 set to 6176 khz or 8192 khz. digital1 set to 12353 khz or 16384 khz. [3:0] not used. - - address (hex): 3a register name cnfg_differential_outputs description (r/w) configures the electrical compatibility of the differential output driver o1 to be 3 v pecl or 3v lvds. default value 1100 0010 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 o1_lvds_pecl bit no. description bit value value description [7:2] not used. - - [1:0] o1_lvds_pecl selection of the electrical compatibility of output o1 between 3 v pecl and 3 v lvds. 00 01 10 11 output o1 disabled. output o1 3 v pecl compatible. output o1 3 v lvds compatible. not used.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 67 www.semtech.com address (hex): 3b register name cnfg_auto_bw_sel description (r/w) register to select automatic bandwidth selection for the t0 dpll path default value 1111 1101 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 auto_bw_sel t0_lim_int bit no. description bit value value description 7 auto_bw_sel bit to select locked bandwidth (reg. 67) or acquisition bandwidth (reg. 69) for the t0 dpll. 1 0 automatically selects either locked or acquisition bandwidth as appropriate. always selects locked bandwidth. [6:4] not used. - - 3t0_lim_int when set to 1 the integral path value of the dpll is limited or frozen when the dpll reaches either min. or max. frequency. this can be used to minimize subsequent overshoot when the dpll is pulling in. note that when this happens, the reported frequency value via current_dpll_freq (reg. 0c, 0d and 07) is also frozen. 1 0 dpll value frozen. dpll not frozen. [2:0] not used. - -
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 68 www.semtech.com address (hex): 3c register name cnfg_nominal_frequency [7:0] description (r/w) bits [7:0] of the register used to calibrate the crystal oscillator used to clock the device. default value 1001 1001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 cnfg_nominal_frequency_value[7:0] bit no. description bit value value description [7:0] cnfg_nominal_frequency_value[7:0] - see register description of reg. 3d ( cnfg_nominal_frequency_value[15:8] ). address (hex): 3d register name cnfg_nominal_frequency [15:8] description (r/w) bits [15:8] of the register used to calibrate the crystal oscillator used to clock the device. default value 1001 1001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 cnfg_nominal_frequency_value[15:8] bit no. description bit value value description [7:0] cnfg_nominal_frequency_value[15:8] this register is used in conjunction with reg. 3c ( cnfg_nominal_frequency_value[7:0] ) to be able to offset the frequency of the cr ystal oscillator by up to +514 ppm and ?771 ppm. the default value represents 0 ppm offset from 12.800 mhz. this value is an unsigned integer. - in order to program the ppm offset of the crystal oscillator frequency, the value in reg. 3c and reg. 3d hex need to be concatenated. this value is an unsigned integer. the value multiplied by 0.0196229 dec. will give the value in ppm. to calculate the absolute value, the default 39321 (9999 hex) needs to be subtracted. address (hex): 3e register name cnfg_holdover_frequency [7:0] description (r/w) bits [7:0] of the manual holdover frequency register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 holdover_frequency_value[7:0] bit no. description bit value value description [7:0] holdover_frequency_value[7:0] - see reg. 3f ( cnfg_holdover_frequency ) for details.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 69 www.semtech.com address (hex): 3f register name cnfg_holdover_frequency [15:8] description (r/w) bits [15:8] of the manual holdover frequency register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 holdover_frequency_value[15:8] bit no. description bit value value description [7:0] holdover_frequency_value[15:8] this value in this register is combined with the value in reg. 3e and bits [2:0] of reg. 40 to represent the programmed holdover frequency of the t0 dpll. this register is designed such that software can read the sts_current_dpll_frequency register (reg. 0c, reg. 0d and reg. 07) and filter the value. the result will then be in a suitable format to simply write back to the cnfg_holdover_frequency register. this register can be programmed to read back the internally averaged holdov er frequency rather than the programmed value, see bit 5 of reg. 40 cnfg_holdover_modes . - in order to calculate the holdover ppm offset of the dpll with respect to the crystal oscillator frequency, the value in reg. 3e and the value in bits [2:0] of reg. 40 need to be concatenated. this value is a 2?s complement signed integer. the value multiplied by 0.0003068 dec. will give the value in ppm.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 70 www.semtech.com address (hex): 40 register name cnfg_holdover_modes description (r/w) register to control the holdover modes of the t0 dpll. default value 1000 1000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 auto_averaging fast_averaging read_average mini_h oldover_mode holdover_frequency_value [18:16] bit no. description bit value value description 7 auto_averaging bit to enable the use of the averaged frequency value during holdover. this bit is overridden by the manual holdover control (bit 4, man_holdover , in reg. 34). 0 1 averaged frequency not us ed, holdover frequency either manual or in stantaneously frozen. averaged frequency us ed, providing manual holdover mode is not engaged. 6 fast_averaging bit to control the rate of averaging of the holdover frequency. fast averaging gives a -3db response point of approximately 8 minutes. slow averaging give a -3db response po int of approximately 110 minutes. 0 1 slow holdover freque ncy averaging enabled. fast holdover frequency averaging enabled. 5 read_average bit to control whether the value read from the holdover_frequency_value register is the value written to that register, or the averaged holdover frequency. this allows software to use the internal averager as part of the holdover algorithm, but use manual holdover mode plus software to enhance the performance. 0 1 value read from holdover_frequency_value is the value written to it. value read from a holdover_frequency_value is either the fast or slow averaged frequency as determined by fast_averaging . [4:3] mini_holdover_mode mini-holdover is a term used to describe the state of the dpll when it is in locked mode, but it has temporarily lost its input. this may be a temporary state, or last for many seconds whilst an input is checked for inactivity. the dpll behaves exactly as in holdover, and the frequency can be determined in the same selection of ways (instantaneously, fast averaged or slow averaged). 00 01 10 11 mini-holdover frequency determined in the same way as for full holdover mode. mini-holdover frequency frozen instantaneously. mini-holdover frequency taken from fast averager. mini-holdover frequency taken from slow averager. [2:0] holdover_frequency_value [18:16] - see reg. 3f ( cnfg_holdover_frequency ) for details.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 71 www.semtech.com address (hex): 41 register name cnfg_dpll_freq_limit [7:0] description (r/w) bits [7:0] of the dpll frequency limit register. default value 0111 0110 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 dpll_freq_limit_value[7:0] bit no. description bit value value description [7:0] dpll_freq_limit_value[7:0] this register defines the ex tent of frequency offset to which either the t0 or the t4 dpll will track a source before limiting- i.e. it represents the pull-in range of the dplls. the offset of the device is determined by the frequency offset of the dpll when compared to the offset of the external crystal oscillator clocking the device. if the oscillator is calibrated using cnfg_nominal_frequency reg. 3c and 3d, then this calibration is automatically taken into account. the dpll frequency limit limits the offset of the dpll when compared to the calibrated oscillator frequency. - in order to calculate the frequency limit in ppm, bits [1:0] of reg. 42 and bits [7:0] of reg. 41 need to be concatenated. this value is a unsigned integer and represents limit both positive and negative in ppm. the value multiplied by 0.078 will give the value in ppm. address (hex): 42 register name cnfg_dpll_freq_limit [9:8] description (r/w) bits [9:8] of the dpll frequency limit register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 dpll_freq_limit_value[9:8] bit no. description bit value value description [7:2] not used. - - [1:0] dpll_freq_limit_value[9:8] - see reg. 41 ( cnfg_dpll_freq_limit ) for details.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 72 www.semtech.com address (hex): 43 register name cnfg_interrupt_mask [7:0] description (r/w) bits [7:0] of the interrupt mask register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sec3 interrupt not masked sec2 interrupt not masked sec1 interrupt not masked bit no. description bit value value description 7 sec3 interrupt not masked mask bit for input sec3 interrupt. 0 1 input sec3 cannot generate interrupts. input sec3 can generate interrupts. [7:2] not used. - - 3 sec2 interrupt not masked mask bit for input sec2 interrupt. 0 1 input sec2 cannot generate interrupts. input sec2 can generate interrupts. 2 sec1 interrupt not masked mask bit for input sec1 interrupt. 0 1 input sec1 cannot generate interrupts. input sec1 can generate interrupts. [1:0] not used. - - address (hex): 44 register name cnfg_interrupt_mask [15:8] description (r/w) bits [15:8] of the interrupt mask register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 operating_ mode interrupt not masked main_ref_failed interrupt not masked sec4 interrupt not masked bit no. description bit value value description 7 operating_mode interrupt not masked mask bit for operating_mode interrupt. 0 1 operating mode cannot generate interrupts. operating mode can generate interrupts. 6 main_ref_failed interrupt not masked mask bit for main_ref_failed interrupt. 0 1 main reference failure cannot generate interrupts. main reference failure can generate interrupts. [5:1] not used. - - 0 sec4 interrupt not masked mask bit for input sec4 interrupt. 0 1 input sec4 cannot generate interrupts. input sec4 can generate interrupts.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 73 www.semtech.com address (hex): 45 register name cnfg_interrupt_mask [23:16] description (r/w) bits [23:16] of the interrupt mask register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_status interrupt not masked bit no. description bit value value description 7not used. - - 6 t4_status mask bit for t4_status interrupt. 0 1 change in t4 status cannot generate interrupts. change in t4 status can generate interrupts. [5:0] not used. - - address (hex): 46 register name cnfg_freq_divn [7:0] description (r/w) bits [7:0] of the division factor for inputs using the divn feature. default value 1111 1111 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 divn_value[7:0] bit no. description bit value value description [7:0] divn_value[7:0] - see reg. 47 ( cnfg_freq_divn ) for details. address (hex): 47 register name cnfg_freq_divn [13:8] description (r/w) bits [13:8] of the division factor for inputs using the divn feature. default value 0011 1111 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 divn_value[13:8] bit no. description bit value value description [7:6] not used. - - [5:0] divn_value[13:8] this register, in conjunction with reg. 46 ( cnfg_freq_divn ) represents the integer value by which to divide inputs that use the divn pre-divider. the divn feature supports input frequencies up to a maximum of 100 mhz; therefore, the maximum value that should be written to this register is 30d3 hex (12499 dec.). use of higher divn values may result in unreliable behavior. - the input frequency will be divided by the value in this register plus 1. i.e. to divide by 8, program a value of 7.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 74 www.semtech.com address (hex): 48 register name cnfg_monitors description (r/w) configuration register controlling several input monitoring and switching options. default value 0000 0101* bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 freq_mon_clk los_flag_on_ tdo ultra_fast_ switch ext_switch pbo_freeze pbo_en freq_monitor_ soft_enable freq_monitor_ hard_enable bit no. description bit value value description 7 freq_mon_clk bit to select the source of the clock to the frequency monitors to be either from the output clock or directly from the crystal oscillator. 0 1 frequency monitors clocked by output of to dpll. frequency monitors clocked by crystal oscillator frequency. 6 los_flag_on_tdo bit to select whether the main_ref_fail interrupt from the t0 dpll is flagged on the tdo pin. if enabled this will not strictly conform to the ieee 1149.1 jtag standard for the function of the tdo pin. when enabled the tdo pin will simply mimic the state of the main_ref_fail interrupt status bit. 0 1 normal mode, tdo complies with ieee 1149.1. tdo pin used to indicate the state of the main_ref_fail interrupt status. this allows a system to have a hardware indica tion of a source failure very rapidly. 5 ultra_fast_switch bit to enable ultra-fast sw itching mode. when in this mode, the device will disqualify a locked-to source as soon as it detects a few missing input cycles. 0 1 currently selected source only disqualified by leaky bucket or frequency monitors. currently selected source disqualified after less than 3 missing input cycles. 4 ext_switch bit to enable external switching mode. when in external switching mode, the device is only allowed to lock to a pair of sources. if the srcsw pin is high , the device will be forced to lock to input sec1 regardless of the signal present on that input. if the srcsw pin is low , the device will be forced to lock to input sec2 regardless of the signal present on that input. * the default value of this bit is dependent on the value of the srcsw pin at power-up. 0 1 normal operation mode. external source switching mode enabled. operating mode of the device is always forced to be ?locked? when in this mode. 3 pbo_freeze bit to control the freez ing of phase build-out operation. if phase build-out has been enabled and there have been some source switches, then the input-output phase relationship of the t0 dpll is unknown. if phase build-ou t is no longer required, then it can be frozen. this will maintain the current input-output phase relationship, but not allow further phase build-out events to take place. simply disabling phase build-out could cause a phase shift in the output, as the t0 dpll re-locks the phase to zero degrees. 0 1 phase build-out not frozen. phase build-out frozen, no further phase build-out events will occur.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 75 www.semtech.com 2 pbo_en bit to enable phase build-out events on source switching. when enabled a phase build-out event is triggered every time the t0 dpll selects a new source- this includes exit ing the holdover or free- run states. 0 1 phase build-out not enabled. t0 dpll locks to zero degrees phase. phase build-out enabled on source switching. 1 freq_monitor_soft_enable control to enable frequency monitoring of input reference sources using soft frequency alarms. 0 1 soft frequency monitor alarms disabled. soft frequency monitor alarms enabled. 0 freq_monitor_hard_enable control to enable frequency monitoring of input reference sources using hard frequency alarms. 0 1 hard frequency monitor alarms disabled. hard frequency monitor alarms enabled. address (hex): 48 (cont...) register name cnfg_monitors description (r/w) configuration register controlling several input monitoring and switching options. default value 0000 0101* bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 freq_mon_clk los_flag_on_ tdo ultra_fast_ switch ext_switch pbo_freeze pbo_en freq_monitor_ soft_enable freq_monitor_ hard_enable bit no. description bit value value description
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 76 www.semtech.com address (hex): 49 register name cnfg_freq_mon_threshold description (r/w) register to set both the hard and soft frequency alarm limits for the monitors on the input reference sources. default value 0010 0011 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 soft_frequency_alarm_threshold h ard_frequency_alarm_threshold bit no. description bit value value description [7:4] soft_frequency_alarm_threshold threshold to trigger the soft frequency alarms in the sts_reference_sources registers. this is only used for monitoring. - to calculate the limit in ppm, add one to the 4-bit value in the register, and multiply by 3.81 ppm. the limit is symmetrical about zero. a value of 0010 bin corresponds to an alarm limit of 11.43 ppm. [3:0] hard_frequency_alarm_threshold threshold to trigger the hard frequency alarms in the s ts_reference_sources registers, which can cause a reference source rejection. - to calculate the limit in ppm, add one to the 4-bit value in the register, and multiply by 3.81 ppm. the limit is symmetrical about zero. a value of 0011 bin corresponds to an alarm limit of 15.24 ppm. address (hex): 4a register name cnfg_current_freq_mon_ threshold description (r/w) register to set both the hard and soft frequency alarm limits for the monitors on the currently selected reference source. default value 0010 0011 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 current_soft_frequency_alarm_threshold c urrent_hard_frequency_alarm_threshold bit no. description bit value value description [7:4] current_soft_frequency_alarm_threshold threshold to trigger the so ft frequency alarm in the sts_reference_sources register applying to the currently selected source.the currently selected source can be monitored for frequency using different limits to all other sources. - to calculate the limit in ppm, add one to the 4-bit value in the register, and multiply by 3.81 ppm. the limit is symmetrical about zero. a value of 0010 bin corresponds to an alarm limit of 11.43 ppm. [3:0] current_hard_frequency_alarm_threshold threshold to trigger the ha rd frequency alarm in the sts_reference_sources register applying to the currently selected source. - to calculate the limit in ppm, add one to the 4-bit value in the register, and multiply by 3.81 ppm. the limit is symmetrical about zero. a value of 0011 bin corresponds to an alarm limit of 15.24 ppm.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 77 www.semtech.com address (hex): 4b register name cnfg_registers_source_select description (r/w) register to select the source of many of the registers. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_t0_select frequency_measurement_channel_select bit no. description bit value value description [7:5] not used. - - 4 t4_t0_select bit to select between the t0 and t4 path for: reg. 0a, 0b ( sts_priority_table) reg. 0c, 0d and 07 ( sts_current_dpll_frequency) reg. 77, 78 ( sts_current_phase) 0 1 t0 path registers selected. t4 path registers selected. [3:0] frequency_measurement_channel_select register to select which input channel the frequency measurement result in reg. 4c ( sts_freq_measurement ) is taken from. 0011 0111 1000 1001 all other values frequency measurement taken from input sec1. frequency measurement taken from input sec2. frequency measurement taken from input sec3. frequency measurement taken from input sec4. not used- refers to no input channel. address (hex): 4c register name sts_freq_measurement description (ro) register from which the frequency measurement result can be read. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 freq_measurement_value bit no. description bit value value description [7:0] freq_measurement_value this represents the value of the frequency measurement on the channel number selected in reg. 4b ( cnfg_registers_source_select ). this value will represent the offset in frequency from the clock to the frequency monitors. this can be either the crystal oscillator to the device, or the output of the t0 dpll as selected in reg. 48 bit 7 cnfg_monitors. - this is an 8-bit 2?s complement signed integer. to calculate the offset in ppm of the selected input channel, this value should be multiplied by 3.81 ppm.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 78 www.semtech.com address (hex): 4d register name cnfg_dpll_soft_limit description (r/w) register to program the soft frequency limit of the two dplls. exceeding this limit will have no effect beyond triggering a flag. default value 1000 1110 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 freq_lim_ph_ loss dpll_soft_limit_value bit no. description bit value value description 7 freq_lim_ph_loss bit to enable the phase lost indication when the dpll hits its hard frequency limit as programmed in reg. 41 and reg. 42 ( cnfg_dpll_freq_limit ). this results in the dpll entering the phase lost state any time the dpll tracks to th e extent of its hard limit. 0 1 phase lost/locked determined normally. phase lost forced when dpll tracks to hard limit. [6:0] dpll_soft_limit_value register to program to wh at extent either of the dplls tracks a source before raising its soft frequency alarm flag (bits 5 and 4 of reg. 09, sts_operating ). this offset is compared to the crystal oscillator frequency taking into account any programmed calibration. - to calculate the ppm offset multiply this 7-bit value by 0.628 ppm. the limit is symmetrical about zero. a value of 0001110 bin is equivalent to 8.79 ppm. address (hex): 50 register name cnfg_upper_threshold_0 description (r/w) register to program the activity alarm setting limit for leaky bucket configuration 0. default value 0000 0110 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration upper_threshold_0_value bit no. description bit value value description [7:0] upper_threshold_0_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 53 ( cnfg_decay_rate_0 ), in which this does not occur, the accumulator is decremented by 1. when the accumulator count reaches the value programmed as the upper_threshold_0_value, the leaky bucket raises an input inactivity alarm. - value at which the leaky bucket will raise an inactivity alarm.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 79 www.semtech.com address (hex): 51 register name cnfg_lower_threshold_0 description (r/w) register to program the activity alarm resetting limit for leaky bucket configuration 0. default value 0000 0100 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration lower_threshold_0_value bit no. description bit value value description [7:0] lower_threshold_0_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 53 ( cnfg_decay_rate_0 ), in which this does not occur, the accumulator is decremented by 1. the lower_threshold_0_value is the value at which the leaky bucket will reset an inactivity alarm. - value at which the leaky bucket will reset an inactivity alarm. address (hex): 52 register name cnfg_bucket_size_0 description (r/w) register to program the maximum size limit for leaky bucket configuration 0. default value 0000 1000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration bucket_size_0_value bit no. description bit value value description [7:0] bucket_size_0_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 53 ( cnfg_decay_rate_0 ), in which this does not occur, the accumulator is decremented by 1. the number in the bucket cannot exceed the value programmed into this register. - value at which the leaky bucket will stop incrementing, even with further inactive periods.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 80 www.semtech.com address (hex): 53 register name cnfg_decay_rate_0 description (r/w) register to program the ?decay? or ?leak? rate for leaky bucket configuration 0. default value 0000 0001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration decay_rate_0_value bit no. description bit value value description [7:2] not used. - - [1:0] decay_rate_0_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in this register, in which this does not occur, the accumulator is decremented by 1. the leaky bucket can be programmed to ?leak? or ?decay? at the same rate as the ?fill? cycle, or effectively at one half, one quarter, or one eighth of the fill rate. 00 01 10 11 bucket decay rate of 1 every 128 ms. bucket decay rate of 1 every 256 ms. bucket decay rate of 1 every 512 ms. bucket decay rate of 1 every 1024 ms. address (hex): 54 register name cnfg_upper_threshold_1 description (r/w) register to program the activity alarm setting limit for leaky bucket configuration 1. default value 0000 0110 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration upper_threshold_1_value bit no. description bit value value description [7:0] upper_threshold_1_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 57 ( cnfg_decay_rate_1 ), in which this does not occur, the accumulator is decremented by 1. when the accumulator count reaches the value programmed as the upper_threshold_1_value, the leaky bucket raises an input inactivity alarm. - value at which the leaky bucket will raise an inactivity alarm.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 81 www.semtech.com address (hex): 55 register name cnfg_lower_threshold_1 description (r/w) register to program the activity alarm resetting limit for leaky bucket configuration 1. default value 0000 0100 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration lower_threshold_1_value bit no. description bit value value description [7:0] lower_threshold_1_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 57 ( cnfg_decay_rate_1 ), in which this does not occur, the accumulator is decremented by 1. the lower_threshold_1_value is the value at which the leaky bucket will reset an inactivity alarm. - value at which the leaky bucket will reset an inactivity alarm. address (hex): 56 register name cnfg_bucket_size_1 description (r/w) register to program the maximum size limit for leaky bucket configuration 1. default value 0000 1000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration bucket_size_1_value bit no. description bit value value description [7:0] bucket_size_1_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 57 ( cnfg_decay_rate_1 ), in which this does not occur, the accumulator is decremented by 1. the number in the bucket cannot exceed the value programmed into this register. - value at which the leaky bucket will stop incrementing, even with further inactive periods.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 82 www.semtech.com address (hex): 57 register name cnfg_decay_rate_1 description (r/w) register to program the ?decay? or ?leak? rate for leaky bucket configuration 1. default value 0000 0001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration decay_rate_1_value bit no. description bit value value description [7:2] not used. - - [1:0] decay_rate_1_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in this register, in which this does not occur, the accumulator is decremented by 1. the leaky bucket can be programmed to ?leak? or ?decay? at the same rate as the ?fill? cycle, or effectively at one half, one quarter, or one eighth of the fill rate. 00 01 10 11 bucket decay rate of 1 every 128 ms. bucket decay rate of 1 every 256 ms. bucket decay rate of 1 every 512 ms. bucket decay rate of 1 every 1024 ms. address (hex): 58 register name cnfg_upper_threshold_2 description (r/w) register to program the activity alarm setting limit for leaky bucket configuration 2. default value 0000 0110 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration upper_threshold_2_value bit no. description bit value value description [7:0] upper_threshold_2_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 5b ( cnfg_decay_rate_2 ), in which this does not occur, the accumulator is decremented by 1. when the accumulator count reaches the value programmed as the upper_threshold_2_value, the leaky bucket raises an input inactivity alarm. - value at which the leaky bucket will raise an inactivity alarm.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 83 www.semtech.com address (hex): 59 register name cnfg_lower_threshold_2 description (r/w) register to program the activity alarm resetting limit for leaky bucket configuration 2. default value 0000 0100 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration lower_threshold_2_value bit no. description bit value value description [7:0] lower_threshold_2_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 5b ( cnfg_decay_rate_2 ), in which this does not occur, the accumulator is decremented by 1. the lower_threshold_2_value is the value at which the leaky bucket will reset an inactivity alarm. - value at which the leaky bucket will reset an inactivity alarm. address (hex): 5a register name cnfg_bucket_size_2 description (r/w) register to program the maximum size limit for leaky bucket configuration 2. default value 0000 1000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration bucket_size_2_value bit no. description bit value value description [7:0] bucket_size_2_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 5b ( cnfg_decay_rate_2 ), in which this does not occur, the accumulator is decremented by 1. the number in the bucket cannot exceed the value programmed into this register. - value at which the leaky bucket will stop incrementing, even with further inactive periods.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 84 www.semtech.com address (hex): 5b register name cnfg_decay_rate_2 description (r/w) register to program the ?decay? or ?leak? rate for leaky bucket configuration 2. default value 0000 0001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration decay_rate_2_value bit no. description bit value value description [7:2] not used. - - [1:0] decay_rate_2_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in this register, in which this does not occur, the accumulator is decremented by 1. the leaky bucket can be programmed to ?leak? or ?decay? at the same rate as the ?fill? cycle, or effectively at one half, one quarter, or one eighth of the fill rate. 00 01 10 11 bucket decay rate of 1 every 128 ms. bucket decay rate of 1 every 256 ms. bucket decay rate of 1 every 512 ms. bucket decay rate of 1 every 1024 ms. address (hex): 5c register name cnfg_upper_threshold_3 description (r/w) register to program the activity alarm setting limit for leaky bucket configuration 3. default value 0000 0110 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration upper_threshold_3_value bit no. description bit value value description [7:0] upper_threshold_3_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 5f ( cnfg_decay_rate_3 ), in which this does not occur, the accumulator is decremented by 1. when the accumulator count reaches the value programmed as the upper_threshold_3_value, the leaky bucket raises an input inactivity alarm. - value at which the leaky bucket will raise an inactivity alarm.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 85 www.semtech.com address (hex): 5d register name cnfg_lower_threshold_3 description (r/w) register to program the activity alarm resetting limit for leaky bucket configuration 3. default value 0000 0100 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration lower_threshold_3_value bit no. description bit value value description [7:0] lower_threshold_3_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 5f ( cnfg_decay_rate_3 ), in which this does not occur, the accumulator is decremented by 1. the lower_threshold_3_value is the value at which the leaky bucket will reset an inactivity alarm. - value at which the leaky bucket will reset an inactivity alarm. address (hex): 5e register name cnfg_bucket_size_3 description (r/w) register to program the maximum size limit for leaky bucket configuration 3. default value 0000 1000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration bucket_size_3_value bit no. description bit value value description [7:0] bucket_size_3_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in reg. 5f ( cnfg_decay_rate_3 ), in which this does not occur, the accumulator is decremented by 1. the number in the bucket cannot exceed the value programmed into this register. - value at which the leaky bucket will stop incrementing, even with further inactive periods.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 86 www.semtech.com address (hex): 5f register name cnfg_decay_rate_3 description (r/w) register to program the ?decay? or ?leak? rate for leaky bucket configuration 3. default value 0000 0001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 leaky bucket configuration decay_rate_3_value bit no. description bit value value description [7:2] not used. - - [1:0] decay_rate_3_value the leaky bucket operates on a 128 ms cycle. if, during a cycle, it detects that an input has either failed or has been erratic, then for each cycle in which this occurs, the accumulator is incremented by 1, and for each period of 1, 2, 4, or 8 cycles, as programmed in this register, in which this does not occur, the accumulator is decremented by 1. the leaky bucket can be programmed to ?leak? or ?decay? at the same rate as the ?fill? cycle, or effectively at one half, one quarter, or one eighth of the fill rate. 00 01 10 11 bucket decay rate of 1 every 128 ms. bucket decay rate of 1 every 256 ms. bucket decay rate of 1 every 512 ms. bucket decay rate of 1 every 1024 ms.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 87 www.semtech.com address (hex): 60 register name cnfg_output_frequency (o2) description (r/w) register to configure and enable the frequencies available on output o2. default value 1000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 output_freq_02 bit no. description bit value value description [7:4] output_freq_02 configuration of the output frequency available at output o2. many of the frequencies available are dependent on the frequencies of the t0 apll and the t4 apll. these are configured in reg. 64 and reg. 65. for more detail see the section on configuring the output frequencies. additionally, for the ethernet frequencies 25 mhz, 50 mhz, 62.5 mhz and 125 mhz, ethernet configuration register cn fg_enet_freq (reg. 20) must be appropriately programmed. bit [6] of reg. 20 enables (1) or disables (0) the ethernet apll. bit [1] of reg. 20 selects (1) or disables (0) the ethernet frequency output at 02. 0000 reg. 20[1] at 0 = output disabled. reg. 20[1] at 1 = 25 mhz (ethernet) 0001 reg. 20[1] at 0 = 2 khz. reg. 20[1] at 1 = 50 mhz (ethernet) 0010 reg. 20[1] at 0 = 8 khz reg. 20[1] at 1 = 62.5 mhz (ethernet) 0011 reg. 20[1] at 0 = digital2 (reg. 39) reg. 20[1] at 1 = 125 mhz (ethernet) 0100 reg. 20[1] at 0 = digital1 (reg. 39) reg. 20[1] at 1 = 25 mhz (ethernet) 0101 reg. 20[1] at 0 = t0 apll frequency/48 reg. 20[1] at 1 = 50 mhz (ethernet) 0110 reg. 20[1] at 0 = t0 apll frequency/16 reg. 20[1] at 1 = 62.5 mhz (ethernet) 0111 reg. 20[1] at 0 = t0 apll frequency/12 reg. 20[1] at 1 = 125 mhz (ethernet) 1000 reg. 20[1] at 0 = t0 apll frequency/8 reg. 20[1] at 1 = 25 mhz (ethernet) 1001 reg. 20[1] at 0 = t0 apll frequency/6 reg. 20[1] at 1 = 50 mhz (ethernet) 1010 reg. 20[1] at 0 = t0 apll frequency/4 reg. 20[1] at 1 = 62.5 mhz (ethernet) 1011 reg. 20[1] at 0 = t4 apll frequency/64 reg. 20[1] at 1 = 125 mhz (ethernet) 1100 reg. 20[1] at 0 = t4 apll frequency/48 reg. 20[1] at 1 = 25 mhz (ethernet) 1101 reg. 20[1] at 0 = t4 apll frequency/16 reg. 20[1] at 1 = 50 mhz (ethernet) 1110 reg. 20[1] at 0 = t4 apll frequency/8 reg. 20[1] at 1 = 62.5 mhz (ethernet) 1111 reg. 20[1] at 0 = t4 apll frequency/4 reg. 20[1] at 1 = 125 mhz (ethernet) [3:0] not used. - -
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 88 www.semtech.com address (hex): 61 register name cnfg_output_frequency (o3) description (r/w) register to configure and enable the frequencies available on output o3. default value 0000 0110 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 output_freq_o3 bit no. description bit value value description [7:4] not used. - - [3:0] output_freq_o3 configuration of the output frequency available at output o3. many of the frequencies available are dependent on the frequencies of the t0 apll and the t4 apll. these are configured in reg. 64 and reg. 65. for more detail see the detailed section on configuring the output frequencies. additionally, for the ethernet frequencies 25 mhz, 50 mhz, 62.5 mhz and 125 mhz, ethernet configuration register cn fg_enet_freq (reg. 20) must be appropriately programmed. bit [6] of reg. 20 enables (1) or disables (0) the ethernet apll. bit [2] of reg. 20 selects (1) or disables (0) the ethernet frequency output at 03. 0000 reg. 20[2] at 0 = output disabled. reg. 20[2] at 1 = 25 mhz (ethernet) 0001 reg. 20[2] at 0 = 2 khz. reg. 20[2] at 1 = 50 mhz (ethernet) 0010 reg. 20[2] at 0 = 8 khz reg. 20[2] at 1 = 62.5 mhz (ethernet) 0011 reg. 20[2] at 0 = digital2 (reg. 39) reg. 20[2] at 1 = 125 mhz (ethernet) 0100 reg. 20[2] at 0 = digital1 (reg. 39) reg. 20[2] at 1 = 25 mhz (ethernet) 0101 reg. 20[2] at 0 = t0 apll frequency/48 reg. 20[2] at 1 = 50 mhz (ethernet) 0110 reg. 20[2] at 0 = t0 apll frequency/16 reg. 20[2] at 1 = 62.5 mhz (ethernet) 0111 reg. 20[2] at 0 = t0 apll frequency/12 reg. 20[2] at 1 = 125 mhz (ethernet) 1000 reg. 20[2] at 0 = t0 apll frequency/8 reg. 20[2] at 1 = 25 mhz (ethernet) 1001 reg. 20[2] at 0 = t0 apll frequency/6 reg. 20[2] at 1 = 50 mhz (ethernet) 1010 reg. 20[2] at 0 = t0 apll frequency/4 reg. 20[2] at 1 = 62.5 mhz (ethernet) 1011 reg. 20[2] at 0 = t4 apll frequency/64 reg. 20[2] at 1 = 125 mhz (ethernet) 1100 reg. 20[2] at 0 = t4 apll frequency/48 reg. 20[2] at 1 = 25 mhz (ethernet) 1101 reg. 20[2] at 0 = t4 apll frequency/16 reg. 20[2] at 1 = 50 mhz (ethernet) 1110 reg. 20[2] at 0 = t4 apll frequency/8 reg. 20[2] at 1 = 62.5 mhz (ethernet) 1111 reg. 20[2] at 0 = t4 apll frequency/4 reg. 20[2] at 1 = 125 mhz (ethernet)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 89 www.semtech.com address (hex): 62 register name cnfg_output_frequency (01 & o4) description (r/w) register to configure and enable the frequencies available on outputs 01 and o4. default value 1000 0100 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 output_freq_o1 output_freq_o4 bit no. description bit value value description [7:4] output_freq_01 configuration of the output frequency available at output o1. many of the frequencies available are dependent on the frequencies of the t0 apll and the t4 apll. these are configured in reg. 64 and reg. 65. for more detail see the section on configuring the output frequencies. additionally, for the ethernet frequencies 25 mhz, 50 mhz, 62.5 mhz and 125 mhz, ethernet configuration register cn fg_enet_freq (reg. 20) must be appropriately programmed. bit [6] of reg. 20 enables (1) or disables (0) the ethernet apll. bit [5] of reg. 20 selects (1) or disables (0) the ethernet frequency output at 01. 0000 reg. 20[5] at 0 = output disabled. reg. 20[5] at 1 = 25 mhz (ethernet) 0001 reg. 20[5] at 0 = 2 khz. reg. 20[5] at 1 = 50 mhz (ethernet) 0010 reg. 20[5] at 0 = 8 khz reg. 20[5] at 1 = 62.5 mhz (ethernet) 0011 reg. 20[5] at 0 = t0 apll/2 reg. 20[5] at 1 = 125 mhz (ethernet) 0100 reg. 20[5] at 0 = digital1 (reg. 39) reg. 20[5] at 1 = 25 mhz (ethernet) 0101 reg. 20[5] at 0 = t0 apll frequency/48 reg. 20[5] at 1 = 50 mhz (ethernet) 0110 reg. 20[5] at 0 = t0 apll frequency/16 reg. 20[5] at 1 = 62.5 mhz (ethernet) 0111 reg. 20[5] at 0 = t0 apll frequency/12 reg. 20[5] at 1 = 125 mhz (ethernet) 1000 reg. 20[5] at 0 = t0 apll frequency/8 reg. 20[5] at 1 = 25 mhz (ethernet) 1001 reg. 20[5] at 0 = t0 apll frequency/6 reg. 20[5] at 1 = 50 mhz (ethernet) 1010 reg. 20[5] at 0 = t0 apll frequency/4 reg. 20[5] at 1 = 62.5 mhz (ethernet) 1011 reg. 20[5] at 0 = t4 apll frequency/64 reg. 20[5] at 1 = 125 mhz (ethernet) 1100 reg. 20[5] at 0 = t4 apll frequency/48 reg. 20[5] at 1 = 25 mhz (ethernet) 1101 reg. 20[5] at 0 = t4 apll frequency/16 reg. 20[5] at 1 = 50 mhz (ethernet) 1110 reg. 20[5] at 0 = t4 apll frequency/8 reg. 20[5] at 1 = 62.5 mhz (ethernet) 1111 reg. 20[5] at 0 = t4 apll frequency/4 reg. 20[5] at 1 = 125 mhz (ethernet)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 90 www.semtech.com [3:0] output_freq_o4 configuration of the output frequency available at output o4. many of the frequencies available are dependent on the frequencies of the t0 apll and the t4 apll. these are configured in reg. 64 and reg. 65. for more detail see the detailed section on configuring the output frequencies. additionally, for the ethernet frequencies 25 mhz, 50 mhz, 62.5 mhz and 125 mhz, ethernet configuration register cn fg_enet_freq (reg. 20) must be appropriately programmed. bit [6] of reg. 20 enables (1) or disables (0) the ethernet apll. bit [4] of reg. 20 selects (1) or disables (0) the ethernet frequency output at 04. 0000 reg. 20[4] at 0 = output disabled. reg. 20[4] at 1 = 25 mhz (ethernet) 0001 reg. 20[4] at 0 = 2 khz. reg. 20[4] at 1 = 50 mhz (ethernet) 0010 reg. 20[4] at 0 = 8 khz reg. 20[4] at 1 = 62.5 mhz (ethernet) 0011 reg. 20[4] at 0 = digital2 (reg. 39) reg. 20[4] at 1 = 125 mhz (ethernet) 0100 reg. 20[4] at 0 = digital1 (reg. 39) reg. 20[43] at 1 = 25 mhz (ethernet) 0101 reg. 20[4] at 0 = t0 apll frequency/48 reg. 20[4] at 1 = 50 mhz (ethernet) 0110 reg. 20[4] at 0 = t0 apll frequency/16 reg. 20[4] at 1 = 62.5 mhz (ethernet) 0111 reg. 20[4] at 0 = t0 apll frequency/12 reg. 20[4] at 1 = 125 mhz (ethernet) 1000 reg. 20[4] at 0 = t0 apll frequency/8 reg. 20[4] at 1 = 25 mhz (ethernet) 1001 reg. 20[4] at 0 = t0 apll frequency/6 reg. 20[4] at 1 = 50 mhz (ethernet) 1010 reg. 20[4] at 0 = t0 apll frequency/4 reg. 20[4] at 1 = 62.5 mhz (ethernet) 1011 reg. 20[4] at 0 = t4 apll frequency/2 reg. 20[4] at 1 = 125 mhz (ethernet) 1100 reg. 20[4] at 0 = t4 apll frequency/48 reg. 20[4] at 1 = 25 mhz (ethernet) 1101 reg. 20[4] at 0 = t4 apll frequency/16 reg. 20[4] at 1 = 50 mhz (ethernet) 1110 reg. 20[4] at 0 = t4 apll frequency/8 reg. 20[4] at 1 = 62.5 mhz (ethernet) 1111 reg. 20[4] at 0 = t4 apll frequency/4 reg. 20[4] at 1 = 125 mhz (ethernet) address (hex): 62 (cont...) register name cnfg_output_frequency (01 & o4) description (r/w) register to configure and enable the frequencies available on outputs 01 and o4. default value 1000 0100 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 output_freq_o1 output_freq_o4 bit no. description bit value value description
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 91 www.semtech.com address (hex): 63 register name cnfg_output_frequency (mfrsync) description (r/w) register to configure and enable the frequencies available on mfrsync output. default value 1100 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 mfrsync_en frsync_en bit no. description bit value value description 7 mfrsync_en register bit to enable the 2 khz sync output (mfrsync). 0 1 output mfrsync disabled. output mfrsync enabled. 6 frsync_en register bit to enable the 8 khz sync output (frsync). 0 1 output frsync disabled. output frsync enabled. [5:0] not used. - - address (hex): 64 register name cnfg_t4_dpll_frequency description (r/w) register to configure the t4 dpll and several other parameters for the t4 path. default value 0000 0101 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_dpll_frequency bit no. description bit value value description [7:3] not used. - - [2:0] t4_dpll_frequency register to configure the frequency of operation of the dpll in the t4 path. the frequency of the dpll will also affect the frequency of the t4 apll which, in turn, affects the frequencies available at outputs o1 - o4 see reg. 60 - reg. 62. it is also possible to not use the t4 dpll at al l, but use the t4 apll to run directly from the t0 dpll output, see reg. 65 ( cnfg_to_dpll_frequency ). if any frequencies are required from the t4 apll then the t4 dpll should not be squelched, as the t4 apll input is squelched and the t4 apll will free run. 000 001 010 011 100 101 110 111 t4 dpll squelched (clock off). 77.76 mhz (oc-n rates), t4 apll frequency = 311.04 mhz. 12e1, t4 apll frequency = 98.304 mhz. 16e1, t4 apll frequency = 131.072 mhz. 24ds1, t4 apll frequency = 148.224 mhz. 16ds1, t4 apll frequency = 98.816 mhz. e3, t4 apll frequency = 274.944 mhz. ds3, t4 apll frequency = 178.944 mhz.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 92 www.semtech.com address (hex): 65 register name cnfg_t0_dpll_frequency description (r/w) register to configure the t0 dpll and several other parameters for the t0 path. default value 0000 0001 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_meas_t0_ ph t4_apll_for_ t0 t0_freq_to_t4_apll t0_dpll_frequency bit no. description bit value value description 7 t4_meas_t0_ph register bit to control the feature to use the t4 path to measure phase offset from the t0 path. when enabled the t4 path is disabled and the phase detector is used to measure the phase between the input to the t0 dpll and the selected t4 input. 0 1 normal- t4 path normal operation. t4 dpll disabled, t4 phase detector used to measure phase between selected t0 input and selected t4 input. 6 t4_apll_for_t0 register bit to select whether the t4 apll takes its input from the t4 dpll or the t0 dpll. if the t0 dpll is selected then the frequency is controlled by bits [5:4], t0_freq_to_t4_apll . 0 1 t4 apll takes its input from the t4 dpll. t4 apll takes its input from the t0 dpll. [5:4] t0_freq_to_t4_apll register to select the t0 frequency driven to the t4 apll when selected by bit 6, t4_apll_for_t0 . 00 01 10 11 12e1, t4 apll frequency = 98.304 mhz. 16e1, t4 apll frequency = 131.072 mhz. 24ds1, t4 apll frequency = 148.224 mhz. 16ds1, t4 apll frequency = 98.816 mhz. 3not used. - - [2:0] t0_dpll_frequency register to configure the frequency of operation of the dpll/apll in the t0 pa th. this register affects the frequencies available at outputs o1 to o4, see reg. 60 - reg. 63. 000 001 010 011 100 101 110 111 77.76 mhz, digital feedback, t0 apll frequency = 311.04 mhz. 77.76 mhz, analog feedback, t0 apll frequency = 311.04 mhz. 12e1, t0 apll frequency = 98.304 mhz. 16e1, t0 apll frequency = 131.072 mhz. 24ds1, t0 apll frequency = 148.224 mhz. 16ds1, t0 apll frequency = 98.816 mhz. not used. not used.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 93 www.semtech.com address (hex): 66 register name cnfg_t4_dpll_bw description (r/w) register to configure the bandwidth of the t4 dpll. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_dpll_bandwidth bit no. description bit value value description [7:2] not used. - - [1:0] t4_dpll_bandwidth register to configure the bandwidth of the t4 dpll. 00 01 10 11 t4 dpll 18 hz bandwidth. t4 dpll 35 hz bandwidth. t4 dpll 70 hz bandwidth. not used. address (hex): 67 register name cnfg_t0_dpll_locked_bw description (r/w) register to configure the bandwidth of the t0 dpll, when phase locked to an input. default value 0000 1101 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t0_dpll_locked_bandwidth bit no. description bit value value description [7:4] not used. - - [3:0] t 0_dpll_locked_bandwidth register to configure the bandwidth of the t0 dpll when locked to an input reference. reg. 3b bit 7 is used to control whether this bandwidth is used all of the time or automatically switched to when phase locked. 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 all other values t0 dpll 0.1 hz locked bandwidth. t0 dpll 0.3 hz locked bandwidth. t0 dpll 0.6 hz locked bandwidth. t0 dpll 1.2 hz locked bandwidth. t0 dpll 2.5 hz locked bandwidth. t0 dpll 4 hz locked bandwidth. t0 dpll 8 hz locked bandwidth. t0 dpll 18 hz locked bandwidth. t0 dpll 35 hz locked bandwidth. t0 dpll 70 hz locked bandwidth. not used.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 94 www.semtech.com address (hex): 69 register name cnfg_t0_dpll_acq_bw description (r/w) register to configure the bandwidth of the t0 dpll, when not phase locked to an input. default value 0000 1111 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t0_dpll_acquisition_bandwidth bit no. description bit value value description [7:4] not used. - - [3:0] t0_dpll_acquisition_bandwidth register to configure the bandwidth of the t0 dpll when acquiring phase lock on an input reference. reg. 3b bit 7 is used to control whether this bandwidth is not used or automatically switched to when not phase locked. 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 all other values t0 dpll 0.1 hz acquisition bandwidth. t0 dpll 0.3 hz acquisition bandwidth. t0 dpll 0.6 hz acquisition bandwidth. t0 dpll 1.2 hz acquisition bandwidth. t0 dpll 2.5 hz acquisition bandwidth. t0 dpll 4 hz acquisition bandwidth. t0 dpll 8 hz acquisition bandwidth. t0 dpll 18 hz acquisition bandwidth. t0 dpll 35 hz acquisition bandwidth. t0 dpll 70 hz acquisition bandwidth. not used.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 95 www.semtech.com address (hex): 6a register name cnfg_t4_dpll_damping description (r/w) register to configure the damping factor of the t4 dpll, along with the gain of phase detector 2 in some modes. default value 0001 0011 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_pd2_gain_alog_8k t4_damping bit no. description bit value value description 7not used. - - [6:4] t4_pd2_gain_alog_8k register to control the gain of the phase detector 2 when locking to a reference of 8 khz or less in analog feedback mode. this setting is only used if automatic gain selection is enabled in reg. 6c bit 7, cnfg_t4_dpll_pd2_gain . - gain value of the phase detector 2 when locking to an 8 khz reference in analog feedback mode. 3not used. - - [2:0] t4_damping register to configure the damping factor of the t4 dpll. the bit values co rresponds to different damping factors, depending on the bandwidth selected. damping factor of 5 being the default (011). the gain peak for the damping factors given in the value description (right) are tabulated below. 001 010 011 100 101 000 110 111 t4 dpll damping factor at the following bandwidths frequency selections: 18 hz 35 hz 70 hz 1.2 1.2 1.2 2.5 2.5 2.5 555 51010 51020 not used. not used. not used. damping factor gain peak 1.2 2.5 5 10 20 0.4 db 0.2 db 0.1 db 0.06 db 0.03 db
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 96 www.semtech.com address (hex): 6b register name cnfg_t0_dpll_damping description (r/w) register to configure the damping factor of the t0 dpll, along with the gain of the phase detector 2 in some modes. default value 0001 0011 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t0_pd2_gain_alog_8k t0_damping bit no. description bit value value description 7not used. - - [6:4] t0_pd2_gain_alog_8k register to control the gain of the phase detector 2 when locking to a reference of 8 khz or less in analog feedback mode. this setting is only used if automatic gain selection is enabled in reg. 6d bit 7, cnfg_t0_dpll_pd2_gain . - gain value of the phase detector 2 when locking to an 8 khz reference in analog feedback mode. 3not used. - - [2:0] t0_damping register to configure the damping factor of the t0 dpll. the bit values co rresponds to different damping factors, depending on the bandwidth selected. damping factor of 5 being the default (011). 001 010 011 100 101 000 110 111 t0 dpll damping factor at the following bandwidths frequency selections: < 4 hz 8 hz 18 hz 35 hz 70 hz 5 2.5 1.2 1.2 1.2 5 5 2.5 2.5 2.5 55555 5551010 5551020 not used. not used. not used. the gain peak for the damping factors given in the value description (right) are tabulated below. damping factor gain peak 1.2 2.5 5 10 20 0.4 db 0.2 db 0.1 db 0.06 db 0.03 db
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 97 www.semtech.com address (hex): 6c register name cnfg_t4_dpll_pd2_gain description (r/w) register to configure the gain of phase detector 2 in some modes for the t4 dpll. default value 1100 0010 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t4_pd2_gain_ enable t4_pd2_gain_alog t4_pd2_gain_digital bit no. description bit value value description 7 t4_pd2_gain_enable 0 1 t4 dpll phase detector 2 not used. t4 dpll phase detector 2 gain enabled and choice of gain determined according to the locking mode: - digital feedback mode - analog feedback mode - analog feedback at 8 khz. [6:4] t4_pd2_gain_alog register to control the ga in of phase detector 2 when locking to a reference, higher than 8 khz, in analog feedback mode. this setting is not used if automatic gain selection is disabled in bit 7, t4_pd2_gain_enable . - gain value of phase detector 2 when locking to a high frequency reference in analog feedback mode. 3not used. - - [2:0] t4_pd2_gain_digital register to control the ga in of phase detector 2 when locking to a reference in digital feedback mode. this setting is always used if automatic gain selection is disabled in bit 7, t4_pd2_gain_enable . - gain value of phase detector 2 when locking to any reference in digital feedback mode.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 98 www.semtech.com address (hex): 6d register name cnfg_t0_dpll_pd2_gain description (r/w) register to configure the gain of phase detector 2 in some modes for the t0 dpll. default value 1100 0010 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 t0_pd2_gain_ enable t0_pd2_gain_alog t0_pd2_gain_digital bit no. description bit value value description 7 t0_pd2_gain_enable 0 1 t0 dpll phase detector 2 not used. t0 dpll phase detector 2 gain enabled and choice of gain determined according to the locking mode: - digital feedback mode - analog feedback mode - analog feedback at 8 khz. [6:4] t0_pd2_gain_alog register to control the ga in of phase detector 2 when locking to a reference, higher than 8 khz, in analog feedback mode. this setting is not used if automatic gain selection is disabled in bit 7, t0_pd2_gain_enable . - gain value of phase detector 2 when locking to a high frequency reference in analog feedback mode. 3not used. - - [2:0] t0_pd2_gain_digital register to control the ga in of phase detector 2 when locking to a reference in digital feedback mode. this setting is always used if automatic gain selection is disabled in bit 7, t0_pd2_gain_enable . - gain value of phase detector 2 when locking to any reference in digital feedback mode. address (hex): 70 register name cnfg_phase_offset [7:0] description (r/w) bits [7:0] of the phase offset control register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 phase_offset_value[7:0] bit no. description bit value value description [7:0] phase_offset_value[7:0] register forming part of the phase offset control. - see reg. 71, cnfg_phase_offset[15:8] for more details.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 99 www.semtech.com address (hex): 71 register name cnfg_phase_offset [15:8] description (r/w) bits [15:8] of the phase offset control register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 phase_offset_value[15:8] bit no. description bit value value description [7:0] phase_offset_value[15:8] register forming part of the phase offset control. if the phase offset register is written to when the dpll is locked to an input, then it is possible that some internal signals become out of synchronization. in order to avoid this, the phas e offset is automatically ?ramped? to the new value. if the phase offset is only ever adjusted when th e device is in holdover, then this is not necess ary, and this automatic ?ramping? can be disabled, see reg. 7c, cnfg_sync_monitor . this register is ignored and has no affect when phase build-out is enabled in either reg. 48 or reg. 76. - the value in this register is to be concatenated with the contents of reg. 70 cnfg_phase_offset[7:0] . this value is a 16-bit 2?s complement signed number. the value multiplied by 6.279 represents the extent of the applied phase offset in picoseconds. the phase offset register is not a control to a ?traditional? delay line. th is number 6.279 actually represents a fractional portion of the period of an internal 77.76 mhz cycle and can, therefore, be represented more accurately as follows. each bit value of the register represents the period of the internal 77.76 mhz clock divided by 2 11 . if, for example, the dpll is locked to a reference that is +1 ppm in frequency with respect to a perfect oscillator, then the peri od, and hence the phase offset, will be decreased by 1 ppm. programming a value of 1024 into the phas e offset register will produce a complete inversion of the 77.76 mhz output clock. note...the exact period of the internal 77.76 mhz clock is determined by the current state of the dpll i.e. in locked mode its accuracy depends on that of the locked to input, in holdover or free-run it depends on the accuracy of the external oscillator.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 100 www.semtech.com address (hex): 72 register name cnfg_pbo_phase_offset description (r/w) register to offset the mean time error of phase build-out events. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 pbo_phase_offset bit no. description bit value value description [7:6] not used. - - [5:0] pbo_phase_offset each time a phase build- out event is triggered, there is an uncertainty of up to 5 ns introduced which translates to a phase hit on the output. the mean error over a large number of events is designed to be zero. this register can be used to introduce a fixed offset in to each pbo event. this will have the effect of moving the mean error positive or negative in time. - the value in this register is a 6-bit 2?s complement number. the value multiplied by 0.101 gives the programmed offset in nano seconds. values greater than +1.4 ns or less than -1.4 ns should not be used as they may cause internal mathematical errors.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 101 www.semtech.com address (hex): 73 register name cnfg_phase_loss_fine_limit description (r/w) register to configure some of the parameters of the t0 dpll phase detector. default value 1010 0010 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 fine_limit_en noact_ph_loss narrow_en phase_loss_fine_limit bit no. description bit value value description 7 fine_limit_en register bit to enable the phase_loss_fine_limit bits [2:0]. when disabled, phase lock/loss is determined by the other means within the device. this must be disabled when multi-ui jitter tolerance is required, see reg. 74, cnfg_phase_loss_course_limit . 0 1 phase loss indication only triggered by other means. phase loss triggered when phase error exceeds the limit programmed in phase_loss_fine_limit , bits [2:0]. 6 noact_ph_loss the dpll detects that an input has failed very rapidly. normally, when the dpll detects this condition, it does not consider phase lock to be lost and will phase lock to the nearest edge (180o) when a source becomes available again, hence giving tolerance to missing cycles. if phase loss is indicated, then frequency and phase locking is instigated (360o locking). this bit can be used to force the dpll to indicate phase loss immediately when no activity is detected. 0 1 no activity on reference does not trigger phase lost indication. no activity triggers phase lost indication. 5 narrow_en (test control bit) set to 1 (default value) 0 1set to 1 [4:3] not used. - - [2:0] phase_loss_fine_limit when enabled by bit 7, this register coarsely sets the phase limit at which the device indicates phase lost or locked. the default value of 2 (010) gives a window size of around 90 - 180o. the phase position of the inputs to the dpll has to be within the window limit for 1 ? 2 seconds before the device indicates phase lock. if it is outside the window for any time then phase loss is immediately indicated. for most cases the default value of 2 (010) is satisfactory. the window size changes in proportion to the value, so a value of 1 (001) will give a narrow phase acceptance or lock window of approximately 45 - 90o. 000 001 010 011 100 101 110 111 do not use. indicates phase loss continuously. small phase window for phase lock indication. recommended value. ) ) ) larger phase window for phase lock indication. ) )
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 102 www.semtech.com address (hex): 74 register name cnfg_phase_loss_coarse_limit description (r/w) register to configure some of the parameters of the t0 dpll phase detector. default value 1000 0101 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 coarse_lim_ phaseloss_en wide_range_en multi_ph_resp phase_loss_coarse_limit bit no. description bit value value description 7 coarse_lim_phaseloss_en register bit to enable the coarse phase detector, whose range is determined by phase_loss_coarse_limit bits [3:0]. this register sets the limit in the number of input clock cycles (ui) that the input phase can move by before the dpll indicates phase lost. 0 1 phase loss not triggered by the coarse phase lock detector. phase loss triggered when phase error exceeds the limit programmed in phase_loss_coarse_limit , bits [3:0]. 6 wide_range_en to enable the device to be tolerant to large amounts of applied jitter and still do direct phase locking at the input frequency rate (up to 77.76 mhz), a wide range phase detector and phase lock detector is employed. this bit enable s the wide range phase detector. this allows the device to be tolerant to, and therefore keep track of, drifts in input phase of many cycles (ui). the range of the phase detector is set by the same register used for the phase loss coarse limit (bits [3:0]). 0 1 wide range phase detector off. wide range phase detector on. 5 multi_ph_resp enables the phase result from the coarse phase detector to be used in the dpll algorithm. bit 6 should also be set when this is activated. the coarse phase detector can measure and keep track over many thousands of in put cycles, thus allowing excellent jitter and wand er tolerance. this bit enables that phase result to be used in the dpll algorithm, so that a large phase measurement gives a faster pull-in of the dpll. if this bit is not set then the phase measurement is limited to 360o which can give a slower pull-in rate at higher input frequencies, but could also be used to give less overshoot. setting this bit in direct locking mode, for example with a 19.44 mhz input, would give the same dynamic response as a 19.44 mhz input used with 8 k locking mode, where the input is divided down internally to 8 khz first. 0 1 dpll phase detector limited to 360o (1 ui). however it will still remember its original phase position over many thousands of ui if bit 6 is set. dpll phase detector also uses the full coarse phase detector result. it can now measure up to: 360o x 8191 ui = 2,948,760o. 4not used. - -
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 103 www.semtech.com [3:0] phase_loss_coarse_limit sets the range of the coarse phase loss detector and the coarse phase detector. when locking to a high frequency signal, and jitter tolerance greater than 0.5 ui is required, then the dpll can be configured to track phase errors over many input clock periods. this is particularly useful with very low bandwidths. this register configures how many ui over which the input phase can be tracked. it also sets the range of the coarse phase loss detector, which can be used with or without the multi-ui phase capture range capability. this register value is used by bits 6 and 7. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100-1111 input phase error tracked over 1 ui. input phase error tracked over 3 ui. input phase error tracked over 7 ui. input phase error tracked over 15 ui. input phase error tracked over 31 ui. input phase error tracked over 63 ui. input phase error tracked over 127 ui. input phase error tracked over 255 ui. input phase error tracked over 511 ui. input phase error tracked over 1023 ui. input phase error tracked over 2047 ui. input phase error tracked over 4095 ui. input phase error tracked over 8191 ui. address (hex): 76 register name cnfg_phasemon description (r/w) register to configure the noise rejection function for low frequency inputs. default value 0000 0110 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 ip_noise_ window bit no. description bit value value description 7 ip_noise_window register bit to enable a window of 5% tolerance around low-frequency inputs (2, 4 and 8 khz). this feature ensures that any edge caused by noise outside the 5% window where the edge is expected will not be considered with in the dpll. this reduces any possible phase hit when a low-frequency connection is removed and contact bounce is possible. 0 1 dpll considers all edges for phase locking. dpll ignores input edges outside a 95% to 105% window. [6:0] not used. - - address (hex): 74 (cont...) register name cnfg_phase_loss_coarse_limit description (r/w) register to configure some of the parameters of the t0 dpll phase detector. default value 1000 0101 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 coarse_lim_ phaseloss_en wide_range_en multi_ph_resp phase_loss_coarse_limit bit no. description bit value value description
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 104 www.semtech.com address (hex): 77 register name sts_current_phase [7:0] description (ro) bits [7:0] of the current phase register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 current_phase[7:0] bit no. description bit value value description [7:0] current_phase bits [7:0] of the current phase register. see reg. 78 sts_current_phase [15:8] for details. - see reg. 78 sts_current_phase [15:8] for details. address (hex): 78 register name sts_current_phase [15:8] description (ro) bits [15:8] of the current phase register. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 current_phase[15:8] bit no. description bit value value description [7:0] current_phase bits [15:8] of the curre nt phase register. this register is used to read either from the phase detector of either the t0 dpll or the t4 dpll, according to reg. 4b bit 4 t4_t0_select . the value is averaged in the phase averager (filter with approx. 100 hz bandwidth) before being made available. - the value in this register should be concatenated with the value in reg. 77 sts_current_phase [7:0] . this 16-bit value is a 2?s complement signed integer. the value multiplied by 0.707 is the averaged value of the current phase error, in degrees, as measured at the dpll?s phase detector. address (hex): 79 register name cnfg_phase_alarm_timeout description (ro) register to configure how long before a phase alarm is raised on an input default value 0011 0010 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 timeout_value bit no. description bit value value description [7:6] not used. - - [5:0] timeout_value phase alarms can only be raised on an input when the t0 dpll is attempting to lock to it. once an input has been rejected due to a phase alarm, there is no way to measure whether it is good again, because it is no longer selected by the dpll. the phase alarms can either remain until reset by software, or timeout after 128 second, as selected in reg. 34 bit 6, phalarm_timeout - this 6-bit unsigned integer represents the length of time before a phase alarm will be raised on an input. the value multiplied by 2 gives the time in seconds. this time value is the time that the controlling state machine will spend in pre-locked, pre-locked2 or phase-lost modes before setting the phase alarm on the selected input.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 105 www.semtech.com address (hex): 7a register name cnfg_sync_pulses description (r/w) register to configure the sync outputs, and select the source for the 2 khz and 8 khz outputs from o1 to o4. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 2k_8k_from_t4 8k_invert 8k_pulse 2k_invert 2k_pulse bit no. description bit value value description 7 2k_8k_from_t4 register to select the source (t0 or t4) for the 2 khz and 8 khz outputs available from o1 to o4. 0 1 2/8 khz on o1 to o4 generated from the t0 dpll. 2/8 khz on o1 to o4 generated from the t4 dpll. [6:4] not used. - - 3 8k_invert register bit to invert the 8 khz output from frsync. 0 1 8 khz frsync output not inverted. 8 khz frsync output inverted. 2 8k_pulse register bit to enable the 8 khz output from frsync to be either pulsed or 50:50 duty cycle. output 03 must be enabled to use ?pulsed output? mode on the frsync output, and then the pulse width on the frsync output will be equal to the period of the output programmed on o3. 0 1 8 khz frsync output not pulsed. 8 khz frsync output pulsed. 1 2k_invert register bit to invert the 2 khz output from mfrsync. 0 1 2 khz mfrsync output not inverted. 2 khz mfrsync output inverted. 0 2k_pulse register bit to enable the 2 khz output from mfrsync to be either puls ed or 50:50 duty cycle. output 03 must be enabled to use ?pulsed output? mode on the mfrsync output, and then the pulse width on the mfrsync output will be equal to the period of the output programmed on o3. 0 1 2 khz mfrsync output not pulsed. 2 khz mfrsync output pulsed.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 106 www.semtech.com address (hex): 7b register name cnfg_sync_phase description (r/w) register to configure the behavior of the synchronization for the external frame reference. default value 0000 0000 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 indep_frsync/ mfrsync sync_oc-n_ rates sync_phase bit no. description bit value value description 7 indep_frsync/mfrsync this allows the option of either maintaining alignment of frsync and other clock outputs during synchronization from the sync2k input, or whether to not maintain alignment to all clocks and so not disturb any of the output clocks 0 1 mfrsync & frsync outputs are always aligned with other output clocks. mfrsync & frsync outputs are independent of other output clocks. 6 sync_oc-n_rates this allows the sync2k input to synchronize the oc-3 derived clocks in order to maintain alignment between the frsync output and output clocks and allow a finer sampling pr ecision of the sync2k input of either 19.44 mhz or 38.88 mhz. 0 1 the oc-n rate clocks are not affected by the sync2k input. the sync2k input is sampled with a 6.48 mhz precision. 6.48mhz should be provided as the input reference clock. allows the sync2k to oper ate with a 19.44 mhz or 38.88 mhz input clock reference. input sampling and output alignment to 19.44 mhz is used when the current clock input is 19.44 mhz, otherwise 38.88 mhz sampling precision is used. [5:2] not used. - [1:0] sync_phase register to control the sampling of the external sync input. nominally the falling edge of the input is aligned with the falling edge of the reference clock. the margin is 0.5 u.i. (unit interval). 00 01 10 11 on target. 0.5 u.i. early 1 u.i. late 0.5 u.i. late.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 107 www.semtech.com address (hex): 7c register name cnfg_sync_monitor description (r/w) register to control the phase offset automatic ramping feature. default value 0010 1011 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 ph_offset_ramp bit no. description bit value value description 7 ph_offset_ramp register bit to force an internal phase offset calibration, see reg. 71, cnfg_phase_offset. the calibration routine is transparent to the user and puts the device in holdover while it internally ramps the phase offset to zero, resets all internal output and feedback dividers and then ramps the phase offset to the current programmed value from reg. 70 or 71., holdover is then turned off. throughout this procedure, no change in output phase offset is visible. 0 1 phase offset automatically ramped from the old value to the new value when there is a change in reg. 70 or 71. start phase offset internal calibration routine. this bit is reset to 0 when this is complete. [6:0] not used. - - address (hex): 7d register name cnfg_interrupt description (r/w) register to configure interrupt output. default value 0000 0010 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 gpo_en tristate_en int_polarity bit no. description bit value value description [7:3] not used. - - 2 gpo_en (interrupt general purpose output). if the interrupt output pin is not required, then setting this bit will allow the pin to be used as a general purpose output. the pin will be driven to the state of the polarity control bit, int_polarity . 0 1 interrupt output pin used for interrupts. interrupt output pin used for gpo purpose. 1 tristate_en the interrupt can be configured to be either connected directly to a processor, or wired together with other sources. 0 1 interrupt pin always driven when inactive. interrupt pin only driven when active, high- impedance when inactive. 0 int_polarity the interrupt pin can be configured to be active high or low . 0 1 active low - pin driven low to indicate active interrupt. active high - pin driven high to indicate active interrupt.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 108 www.semtech.com address (hex): 7e register name cnfg_protection description (r/w) protection register to protect against erroneous software writes. default value 1000 0101 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 protection_value bit no. description bit value value description [7:0] protection_value this register can be used to ensure that the software writes a specific value to this register, before being able to modify any other register in the device. three modes of protection are offered, (i) protected (ii) fully unprotected (iii) single unprotected. when protected, no other register in the device can be written to. when fully unprotected, any writeable register in the device can be written to. when single unprotected, only one register can be written before the device automatically re-protects itself. 0000 0000 ? 1000 0100 1000 0101 1000 0110 1000 0111 ? 1111 1111 protected mode. fully unprotected. single unprotected. protected mode.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 109 www.semtech.com jtag the jtag connections on the ACS8522BT allow a full boundary scan to be made. the jtag implementation is fully compliant to ieee 1149.1, with the following minor exceptions, and the user should refer to the standard for further information. 1. the output boundary scan cells do not capture data from the core, and so do not support intest. however this does not affect board testing. 2. in common with some other manufacturers, pin trst is internally pulled low to disable jtag by default. the standard is to pull high . the polarity of trst is as the standard: trst high to enable jtag boundary scan mode, trst low for normal operation. the jtag timing diagram is shown in figure 14 . over-voltage protection the ACS8522BT may require over-voltage protection on input reference clock ports according to itu recommendation k.41. semtech protection devices are recommended for this purpose (see separate semtech data book). esd protection suitable precautions should be taken to protect against electrostatic damage during handling and assembly. this device incorporates esd protection structures that protect the device against esd damage at esd input levels up to at least +/- 1kv using the human body model (hbd) mil-std-883d method 3015.7, for all pins. latchup protection this device is protected against latchup for input current pulses of magnitude up to at least 100 ma to jedec standard no. 78 august 1997. figure 14 jtag timing electrical specifications table 22 jtag timing (see figure 14 ) parameter symbol minimum typical maximum units cycle time t cyc 50 - - ns tms/tdi to tck rising edge time t sur 3- -ns tck rising to tms/tdi hold time t ht 23 - - ns tck falling to tdo valid t dod --5ns f8110d_022jtagtiming_01 tck tms tdi t sur t ht tdo t dod t cyc
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 110 www.semtech.com maximum ratings important note: the abso lute maximum ratings ( table 23 ) are stress ratings only, and functional operation of the device at conditions other than those indicated in table 24 and elsewhere are not implied. exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. operating conditions dc characteristics table 23 absolute maximum ratings parameter symbol minimum maximum units supply voltage vdd1, vdd2, vdd3, vdd4, vdd5, vdd6, vdd7, vd1+, vd2+,vd3+, va1+, va2+, va3+, vdd_diff v dd -0.5 3.7 v input voltage (non-supply pins) v in -5.5v output voltage (non-supply pins) v out -5.5v ambient operating temperature range t a -40 +85 o c storage temperature t stor -50 +150 o c table 24 operating conditions parameter symbol minimum typical maximum units power supply (dc voltage) vdd1, vdd2, vdd3, vdd4, vdd5, vdd6, vdd7, vd1+, vd2+,vd3+, va1+, va2+, va3+, vdd_diff v dd 3.0 3.3 3.6 v power supply (dc voltage) vdd5v v dd5v 3.0 3.3/5.0 5.5 v ambient temperature range t a -40 - +85 o c supply current (1) (typical - one 19 mhz output) i dd - 120 212 ma supply current (typical - one 25 mhz output) i dd - 137 240 ma total power dissipation p tot - 452 864 mw 1. measured with ethernet pll disabled. table 25 dc characteristics: ttl input port across all operating conditions, unless otherwise stated parameter symbol minimum typical maximum units v in high v ih 2- -v v in low v il --0.8v input current i in --10 ??
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 111 www.semtech.com note: (i) with 50 ? load on each pin to v dd -2 v, i.e. 82 ? to gnd and 130 ? to v dd . table 26 dc characteristics: ttl input port with internal pull-up across all operating conditions, unless otherwise stated parameter symbol minimum typical maximum units v in high v ih 2- -v v in low v il --0.8v pull-up resistor pu 25 - 95 k ? input current i in - - 120 ?? table 27 dc characteristics: ttl input port with internal pull-down across all operating conditions, unless otherwise stated parameter symbol minimum typical maximum units v in high v ih 2- -v v in low v il --0.8v pull-down resistor (except tck input) pd 25 - 95 k ? pull-down resistor (tck input only) pd 12.5 - 47.5 k ? input current i in - - 120 ?? table 28 dc characteristics: ttl output port across all operating conditions, unless otherwise stated parameter symbol minimum typical maximum units v out low (l ol = 4 ma) v ol 0-0.4v v out high (l ol = 4 ma) v oh 2.4 - - v drive current id - - 4 ma table 29 dc characteristics: pecl output port across all operating conditions, unless otherwise stated parameter symbol minimum typical maximum units pecl output low voltage (note (i)) v olpecl v dd -2.10 - v dd -1.62 v pecl output high voltage (note (i)) v ohpecl v dd -1.25 - v dd -0.88 v pecl output differential voltage (note (i)) v odpecl 580 - 900 mv
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 112 www.semtech.com figure 15 recommended line term ination for pecl output ports note: (i) with 100 ?? load between the differential outputs. figure 16 recommended line term ination for lvds output port table 30 dc characteristics: lvds output port across all operating conditions, unless otherwise stated parameter symbol minimum typical maximum units lvds output high voltage (note (i)) v ohlvds --1.585v lvds output low voltage (note (i)) v ollvds 0.885 - - v lvds differential output voltage v odlvds 250 - 450 mv lvds change in magnitude of differential output voltage for complementary states (note (i)) v doslvds --25mv lvds output offset voltage temperature = 25 o c (note (i)) v oslvds 1.125 - 1.275 v o1pos o1neg f8522d_024pecl_02 z 0 = 50 z 0 = 50 v dd = +3.3 v z 0 = transmission line impedance fully programmable output frequencies dd v gnd 130 82 130 82 o1pos o1neg f8522d_025lvds_02 z 0 = 50 ? z 0 = 50 ? z 0 = transmission line impedance fully programmable output frequencies 100 ?
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 113 www.semtech.com jitter performance output jitter generation measured over 60 second inte rval, ui pk-pk max measured using c-mac e2747 12.800 mhz tcxo on ict flexacom tester. table 31 output jitter generation test definition conditio ns jitter spec ACS8522BT jitter specification filter bandwidth i/p freq lock mode ui ui (typ) g813 for 155 mhz o/p option 1 65 khz - 1.3 mhz 4 hz 19 mhz direct lock 0.1 pk-pk 0.067 pk-pk 8k lock 0.065 pk-pk g813 & g812 for 2.048 mhz option 1 20 hz - 100 khz 4 hz 2.048 mhz 8k lock 0.05 pk-pk 0.012 pk-pk g813 for 155 mhz o/p option 2 12 khz - 1.3 mhz 18 hz 19 mhz direct lock/ 8k lock 0.1 pk-pk 0.072 pk-pk 12 khz - 1.3 mhz 8 hz 19 mhz direct lock/ 8k lock 0.1 pk-pk 0.072 pk-pk 12 khz - 1.3 mhz 4 hz 19 mhz direct lock/ 8k lock 0.1 pk-pk 0.078 pk-pk 12 khz - 1.3 mhz 2.5 hz 19 mhz direct lock/ 8k lock 0.1 pk-pk 0.078 pk-pk 12 khz - 1.3 mhz 1.2 hz 19 mhz direct lock/ 8k lock 0.1 pk-pk 0.078 pk-pk 12 khz - 1.3 mhz 0.6 hz 19 mhz direct lock/ 8k lock 0.1 pk-pk 0.076 pk-pk g812 for 1.544 mhz o/p 10 hz - 40 khz 4 hz 1.544 mhz 8k lock 0.05 pk-pk 0.006 pk-pk g812 for 155 mhz electrical 500 hz - 1.3 mhz 4 hz 19 mhz 8k lock 0.5 pk-pk 0.118 pk-pk g812 for 155 mhz electrical 65 khz - 1.3 mhz 4 hz 19 mhz 8k lock 0.075 pk-pk 0.065 pk-pk ets-300-462-3 for 2.048 mhz sec o/p 20 hz - 100 khz 4 hz 2.048 mhz 8k lock 0.5 pk-pk 0.012 pk-pk ets-300-462-3 for 2.048 mhz sec o/p 49 hz - 100 khz 4 hz 2.048 mhz 8k lock 0.2 pk-pk 0.012 pk-pk ets-300-462-3 for 2.048 mhz ssu o/p 20 hz - 100 khz 4 hz 2.048 mhz 8k lock 0.05 pk-pk 0.012 pk-pk ets-300-462-5 for 155 mhz o/p 500 hz - 1.3 mhz 4 hz 19 mhz 8k lock 0.5 pk-pk 0.118 pk-pk ets-300-462-5 for 155 mhz o/p 65 khz - 1.3 mhz 4 hz 19 mhz 8k lock 0.1 pk-pk 0.067 pk-pk gr-253-core net i/f, 51.84 mhz o/p 100 hz - 0.4 mhz 4 hz 19 mhz 8k lock 1.5 pk-pk 0.027 pk-pk gr-253-core net i/f, 51.84 mhz o/p 20 khz to 0.4 mhz 4 hz 19 mhz 8k lock 0.15 pk-pk 0.017 pk-pk gr-253-core net i/f, 155 mhz o/p 500 hz - 1.3 mhz 4 hz 19 mhz 8k lock 1.5 pk-pk 0.118 pk-pk gr-253-core net i/f, 155 mhz o/p 65 khz - 1.3 mhz 4 hz 19 mhz 8k lock 0.15 pk-pk 0.067 pk-pk gr-253-core cat ii elect i/f, 155 mhz 12 khz - 1.3 mhz 4 hz 19 mhz 8k lock 0.1 pk-pk 0.076 pk-pk 0.01 rms 0.006 rms
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 114 www.semtech.com note...this table is only for comparing th e ACS8522BT output jitter performance against values and quoted in various specificat ions for given conditions. it should not be used to infer compli ance to any other aspects of these specifications. gr-253-core cat ii elect i/f, 51.84 mhz 12 khz - 400 khz 4 hz 19 mhz 8k lock 0.1 pk-pk 0.018 pk-pk 0.01 rms 0.003 rms gr-253-core ds1 i/f, 1.544 mhz 10 hz - 40 khz 4 hz 1.544 mhz 8k lock 0.1 pk-pk 0.001 pk-pk 0.01 rms <0.001 rms at&t 62411 for 1.544 mhz 10 hz - 8 khz 4 hz 1.544 mhz 8k lock 0.02 rms <0.001 rms at&t 62411 for 1.544 mhz 8 hz - 40 khz 4 hz 1.544 mhz 8k lock 0.025 rms <0.001 rms at&t 62411 for 1.544 mhz 10 hz - 40 khz 4 hz 1.544 mhz 8k lock 0.025 rms <0.001 rms at&t 62411 for 1.544 mhz broadband 4 hz 1.544 mhz 8k lock 0.05 rms <0.001 rms g-742 for 2.048 mhz dc - 100 khz 4 hz 2.048 mhz 8k lock 0.25 rms 0.012 rms g-742 for 2.048mhz 18 khz - 100 khz 4 hz 2.048 mhz 8k lock 0.05 pk-pk 0.012 pk-pk g-736 for 2.048mhz 20 hz - 100 khz 4 hz 2.048 mhz 8k lock 0.05 pk-pk 0.012 pk-pk gr-499-core & g824 for 1.544 mhz 10 hz - 40khz 4 hz 1.544 mhz 8k lock 5.0 pk-pk 0.006 pk-pk gr-499-core & g824 for 1.544 mhz 8 khz - 40khz 4 hz 1.544 mhz 8k lock 0.1 pk-pk 0.006 pk-pk gr-1244-core for 1.544 mhz > 10 hz 4 hz 1.544 mhz 8k lock 0.05 pk-pk 0.006 pk-pk 25 mhz 12khz to 1.3mhz 8khz 19mhz direct see [20] 0.021 p-p 50 mhz 12khz to 1.3mhz 8khz 19mhz direct see [20] 0.025 p-p 62.5 mhz 12khz to 1.3mhz 8khz 19mhz direct see [20] 0.035 p-p 125 mhz 12khz to 1.3mhz 8khz 19mhz direct see [20] 0.066 p-p table 31 output jitter generation test definition conditio ns jitter spec ACS8522BT jitter specification filter bandwidth i/p freq lock mode ui ui (typ)
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 115 www.semtech.com input/output timing figure 17 input/output timing with phase build-out off f8523d_021ip_optiming_02 input/output delay output min/max phase alignment (frsync alignment switched on) 8 khz input 8 khz output 6.48 mhz input 6.48 mhz output 19.44 mhz input 25.92 mhz input 38.88 mhz input 51.84 mhz input 77.76 mhz input 19.44 mhz output 38.88 mhz output 51.84 mhz output 77.76 mhz output 25.92 mhz output +8.2 1.5 ns +4.7 1.5 ns +4.3 1.5 ns +4.7 1.5 ns +4.6 1.5 ns +3.0 1.5 ns +5.3 1.5 ns 8 khz mfrsync (2 khz) frsync (8 khz) 2 khz ds1 (1.544 mhz) e1 (2.048 mhz) 6.48 mhz 19.44 mhz 25.92 mhz 38.88 mhz 51.84 mhz 77.76 mhz 155.52 mhz -1.2 0.5 ns -0.4 0.5 ns ds3 (44.736 mhz) e3 (34.368 mhz) 311.04 mhz -0.0 0.5 ns -1.2 1.25 ns -1.2 1.25 ns -3.75 1.25 ns -3.75 1.25 ns -3.75 1.25 ns -3.75 1.25 ns -3.75 1.25 ns -3.75 1.25 ns -3.75 1.25 ns -3.75 1.25 ns -3.75 1.25 ns -3.75 1.25 ns
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 116 www.semtech.com figure 18 lqfp package thermal conditions the device is rated for full temperature range when this package is used with a pcb of four layers or more. copper coverage must exceed 50%. all pins mu st be soldered to the pcb. maximum operating temperature must be reduced when the device is used with a pcb with less than these requirements. package information
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 117 www.semtech.com figure 19 typical 64 pin lqfp footprint notes: (i) solderable to this limit. (ii) square package - dimensions apply in both x and y directions. (iii) typical example. the user is re sponsible for ensuring compatibility with pcb manufactur ing process, etc.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 118 www.semtech.com figure 20 simplified application schematic application information
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 119 www.semtech.com apll analogue phase locked loop bits building integrated timing supply dfs digital frequency synthesis dpll digital phase locked loop ds1 1544 kbit/s interface rate dto discrete time oscillator e1 2048 kbit/s interface rate i/o input - output los loss of signal lqfp low profile quad flat pack lvds low voltage differential signal mtie maximum time interval error ne network element ocxo oven controlled crystal oscillator pbo phase build-out pdh plesiochronous digital hierarchy pecl positive emitter coupled logic pfd phase and frequency detector pll phase locked loop por power-on reset ppb parts per billion ppm parts per million pk-pk peak-to-peak rms root-mean-square ro read only r/w read/write sdh synchronous digital hierarchy sec sdh/sonet equipment clock sets synchronous equipment timing source sonet synchronous optical network ssu synchronization supply unit stm synchronous transport module tdev time deviation tcxo temperature compensated crystal oscillator ui unit interval xo crystal oscillator [1] ansi t1.101-1999 (1999) synchronization interface standard. [2] at & t 62411 (12/1990) accunet ? t1.5 service description and interface specification. [3] etsi ets 300 462-3, (01/1997) transmission and multiplexing (tm); generic requirements for synchronization networks; part 3: the control of jitter and wander within synchronization networks. [4] etsi ets 300 462-5 (09/1996) transmission and multiplexing (tm); generic requirements for sync hronization networks; part 5: timing characteristics of slave clocks suitable for operation in synchronous digital hierarchy (sdh) equipment. [5] ieee 1149.1 (1990) standard test access po rt and boundary-scan architecture. [6] itu-t g.703 (10/1998) physical/electrical characterist ics of hierarchical digital interfaces. [7] itu-t g.736 (03/1993) characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s. [8] itu-t g.742 (1988) second order digital multiplex equipment operating at 8448 kbit/s, and using positive justification. [9] itu-t g.783 (10/2000) characteristics of synchronous digital hierarchy (sdh) equipment functional blocks. [10] itu-t g.812 (06/1998) timing requirements of slave clocks suitable for use as node clocks in synchronization networks. [11] itu-t g.813 (08/1996) timing characteristics of sdh equipment slave clocks (sec). [12] itu-t g.822 (11/1988) controlled slip rate objectives on an international digital connection. [13] itu-t g.823 (03/2000) the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy. acronyms and abbreviations references and asso ciated documents
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 120 www.semtech.com [14] itu-t g.824 (03/2000) the control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy. [15] itu-t g.825 (03/2000) the control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (sdh). [16] itu-t k.41 (05/1998) resistability of internal inte rfaces of telecommunication centres to surge overvoltages. [17] telcordia gr-253-core, issue 3 (09/ 2000) synchronous optical network (sonet) transport systems: common generic criteria. [18] telcordia gr-499-core, issue 2 (12/1998) transport systems generic requirements (tsgr) common requirements. [19] telcordia gr-1244-core, issue 2 (12/2000) clocks for the synchronized network: common generic criteria. [20] itu-t g.8262 (draft) timing characteristics of synchronous ethernet equipment slave clock (eec). semtech and the semtech s logo are registered trademarks of semtech corporation. accunet ? is a registered trademark of at & t. c-mac is a registered trademark of c-mac microtechnology - a division of solectron corporation. ict flexacom is a registered trademark of ict electronics. motorola is a registered trademark of motorola, inc. telcordia is a registered trademark of telcordia technologies. trademark acknowledgements
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 121 www.semtech.com the revision status of the datasheet, as shown in the center of the datasheet header bar, may be draft, preliminary or final, and refers to the status of the device (not the datasheet) within the design cycle. draft status is used when the design is being realized but is not yet physically available, and the datasheet content reflects the intention of the design. the datasheet is raised to preliminary status when initial prototype devices are ph ysically available, and the datasheet content more accurately represents the realization of the design. the datasheet is only raised to final status after the device has been fully characterized, and the datasheet content updated with measured, rather than simulated parameter values. this is a final release (revision 1.00) of the ACS8522BT datasheet. changes made for this document revision are given in table 32 , together with a summary of previous revisions. for specific change s between earlier revisions, refer (where available) to those earlier revisions. always use the current version of the datasheet. revision status/history table 32 revision history revision reference description of changes 1.00/april 2010 all pages first rele ase of preliminary datasheet.
ACS8522BT esets advanced comms & sensing final datasheet revision 1.00/april 2010? semtec h corp. page 122 www.semtech.com disclaimers life support - this product is not designed or inte nded for use in life support equipment, devices or systems, or other critical applications, and is not authorized or warranted for such use. right to change - changes may be made to this product without notice. cu stomers are advised to obtain the latest version of the relevant information before placing orders. compliance to relevant standards - operation of this device is subject to the user ?s implementation and desig n practices. it is the responsibility of the user to ensu re equipment using this device is compliant to any relevant standards. semtech corporation advanced co mmunications & sensing products ordering information table 33 parts list part number description ACS8522BT esets synchronous equipment timing source for stratum 3/4e/4, smc and ethernet systems. lead (pb)-free, halogen fr ee, rohs and weee compliant. contact information e-mail: sales@semtech.com acsupport@semtech.com internet: http://www.semtech.com usa 200 flynn road, camarillo, ca 93012-8790. tel: +1 805 498 2111 fax: +1 805 498 3804 far east 12f, no. 89 sec. 5, nanking e. road, taipei, 105, twn, r.o.c. tel: +886 2 2748 3380 fax: +886 2 2748 3390 europe semtech ltd., units 2 & 3, park court, premier way, abbey park industrial estate, romsey, hampshire, so51 9dn. tel: +44 (0)1794 527 600 fax: +44 (0)1794 527 601 iso9001 certified

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